Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual page 16

DAC Example
1. Write 1 into the DAC/ADC TDD mode pin register.
• SetTDDRTSPinCtrl 1 0x0001 enables the TDD on DAC tile 0 channel 0.
• SetTDDRTDPinCtrl DAC/ADC Channel_mask to 1 for DAC and 0 for ADC. Channel mask
bit 0 = DAC0, bit 1 DAC1, etc.
2. Write the symbol length, guard band length, and symbol type registers.
• SetTDDRTSSlot 0 1000 0x01f: guard band 0, symbol length 1000, half DL, half UL.
3. At this stage, the channels selected in step 1 are operating in TDD mode.
4. An immediate trigger can be issued.
5. To stop the TDD RTS pin assertion/deassertion, SetTDDRTSPinCtrl 10x0000
The following figure shows a representation of the frames in the DAC example.
Figure 10: DAC Example Frames and Symbols Representation
Dual ADC Example
1. Write the symbol length, guard band length, and symbol type registers.
• SetTDDRTSSlot 0 1000 0x01f: guard band 0, symbol length 1000, half DL, half UL.
2. Write 1 into the ADC TDD mode pin register.
• SetTDDRTSPinCtrl 0 0x0030 enables the TDD on ADC tile 1 channel 0 for dual ADC.
• As the ADC is a dual ADC, the two TDD RTS pins need to be driven High.
3. At this stage, the channels selected in step 1 are operating in TDD mode.
4. To set up an ADC trigger on a specific frame and symbol:
• Write symbol and frame trigger registers.
SetTDDRTSTrigSlot 5 5.
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SetTDDRTSTrigSlot symbol frame.
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UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
DL DL
Frame #1 of Frame #2 of
N Symbols N Symbols
UL UL
Frame #6 of Frame #7 of
N Symbols N Symbols
DL DL
Frame #3 of Frame #4 of
N Symbols N Symbols
UL UL
Frame #8 of Frame #9 of
N Symbols N Symbols
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Chapter 3: Hardware Design
DL
Frame #5 of
N Symbols
UL
Frame #10 of
N Symbols
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