HP 70427A User Manual page 504

Block Diagram
YIG-Tuned-Filter (YTF) and GaAs FET Amplifier Driver Assembly
The adaptive filter cut-off frequency is switchable between 0.03 Hz for
normal operation and 550 Hz when changing frequency. The adaptive filter
reduces the 110 nV/Hz reference and DAC noise to less than 10 nV/Hz at 0.3
Hz.
The filtered output is the reference for a precision voltage-to-current
converter. The voltage-to-current gain is 40 mA/V, with an output range of 0
to 400 mA. The conversion reference for the converter is a precision 25Ω, 25
W resistor. The resistors temperature stability is 2 ppm/°C. This corresponds
to a 20 kHz/°C frequency drift at 10 GHz. The resistor is mounted to the
microwave deck plate heatsink to reduce its thermal rise due to power
dissipation.
The voltage-to-current conversion is produced by comparing the voltage
across the conversion reference resistor with the input voltage from the
adaptive filter. Since the gate current of an NMOS transistor is essentially 0
(less than 100 nA), the drain current is equal to the source current measured
across the conversion reference.
The OP-77 op-amp (U22) used in the voltage-to-current converter dominates
its low frequency noise. The OP-77 has a typical input noise of 10.5 nV/Hz.
This amplifier was selected mainly for its very low input bias current,
typically less than 1.2 nA. The 1.2 nA bias current produces a 615 μV
voltage drop across the, 511 kΩ (R48), adaptive filter's input resistor when
ever the noise filter is in. This voltage drop corresponds to a 1.84 MHz shift
in frequency.
The noise degradation caused by U22 is controlled at higher frequencies by
controlling the loop bandwidth of the voltage- to-current converter. A pole at
0 Hz, in the response of U22, sets the converter's loop bandwidth to 1.5 kHz.
This integrator limits the noise degradation to 11.5 nV/Hz (462 pA/Hz at the
output) beyond 1.5 kHz.
The converter output current is controlled by an N-Channel Enhancement
Mode Power MOS FET (Q7), driven by the op-amp U22. The MOS FET
will dissipate up to 75 W, with V = 120 V, and I = 10 A. The gate
dss d
threshold voltage is 4 V .
max
The advantage of a power MOS FET is the low drive current requirement.
The gate leakage current is 100 nA max. The disadvantage is that its gate
capacitance is 850 pF, and the drive voltage must be at least 4 volts greater
than the source for current to flow.
The voltage-to-current converter op-amp (U22) is unstable driving the
capacitive gate of the MOS FET directly. Amplifier stability is insured by
driving the MOS FET through the 562Ω resistor (R51). This insures the
op-amp stability, but an additional pole is added to the voltage-to-current
converter loop response at 333 kHz. This pole will reduce all conversion
noise at 6 dB/octave beyond 333 kHz, but in order to maintain loop stability
this pole must be compensated for. The 562Ω resistor also allows a clamping
HP 70427A/HP 70428A User's Guide 13-69