Table of Contents
Advertisement
Once the lead/lag pole frequency is determined, the integrator zero
frequency is also set, where:
The integrator gain at the PLL bandwidth is:
where:
Integratorgain
Figure 13-4
600 MHz Phase Locked Loop Integrator
BWdesired
-----------------------------
=
F
=
zero
100
BW
------------------------------------------------- -
=
------------------------------------------------- -
IntegratorGain
(
R
+
R
1
=
----------------------- - atthePLLbandwidth
R
1
HP 70427A/HP 70428A User's Guide 13-25
Block Diagram
600 MHz Reference Loop (A7A2)
1
F
=
------------------------------------- -
(
pole
2πC
R
+
R
1
1
(
)
first order desired
(
)
BW
first order
Lead\LagGain
)
2
)
2
Advertisement
Table of Contents
