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ADT7460
ADT7460 REGISTER SUMMARY
Tabl
e 41
. AD 7460 Registers
T
Addre
ss
R/W
Description
0x20
R
2.5 V Reading
0x22
R
V
Reading
CC
0x25
R
Remote 1 Temperature
0x26
R
Local Temperature
0x27
R
Remote 2 Temperature
0x28
R
TACH1
Low Byte
0x29
R
TACH1 High Byte
0x2A
R
TACH2 Low Byte
0x2B
R
TACH2 High Byte
0x2C
R
TACH3 Low Byte
0x2D
R
TACH3 High Byte
0x2E
R
TACH4 Low Byte
0x2F
R
TACH4 High Byte
0x30
R/W
PWM1 Current Duty Cycle
0x31
R/W
PWM2 Current Duty Cycle
0x32
R/W
PWM3 Current Duty Cycle
0x33
R/W
Remote 1 Operating Point
0x34
R/W
Local Temp Operating Point
0x35
R/W
Remote 2 Operating Point
0x36
R/W
Dynamic T
Control Reg. 1
MIN
0x37
R/W
Dynamic T
Control Reg. 2
MIN
0x3D
R
Device ID Register
0x3E
R
Company ID Number
0x3F
R
Revision Number
0x40
R/W
Configuration Register 1
0x41
R
Interrupt Status Register 1
0x42
R
Interrupt Status Register 2
0x44
R/W
2.5 V L
ow Limi
t
0x45
R/W
2.5 V H
igh Limit
0x48
R/W
V
Low
Limit
CC
0x49
R/W
V
Hig
h Limit
CC
0x4E
R/W
Remote 1 Temp Low Limit
0x4F
R/W
Remote 1 Temp High Limit
0x50
R/W
Local Temp Low Limit
0x51
R/W
Local Temp High Limit
0x52
R/W
Remote 2 Temp Low Limit
0x53
R/W
Remote 2 Temp High Limit
0x54
R/W
TACH1 Minimum Low Byte
0x55
R/W
TACH1 Minimum High Byte
0x56
R/W
TACH2 Minimum Low Byte
0x57
R/W
TACH2 Minimum High Byte
0x58
R/W
TACH3 Minimum Low Byte
0x59
R/W
TACH3
Minimu
m High Byte
0x5A
R/W
TACH4
Minimum Low
0x5B
R/W
TACH4
Minimum High
0x5C
R/W
PWM1
Configuration
Registe
r
0x5D
R/W
PWM2 Configuration
Register
0x5E
R/W
PWM3 Configuration
Register
0x5F
R/W
Remote 1 T
/PWM 1 Freq.
RANGE
0x60
R/W
Local T
/PWM 2 Freq.
RANGE
0x61
R/W
Remote 2 T
/PWM 3 Freq.
RANGE
0x62
R/W
Enhance Acoustics Reg. 1
0x63
R/W
Enhance Acoustics Reg. 2
0x64
R/W
PWM1 Min Duty Cycle
0x65
R/W
PWM2 Min Duty Cycle
0x66
R/W
PWM3 Min Duty Cycle
Bit
7
Bit
6
Bit
5
9
8
7
9
8
7
9
8
7
9
8
7
9
8
7
7
6
5
15
14
13
7
6
5
15
14
13
7
6
5
15
14
13
7
6
5
15
14
13
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
R2T
LT
R1T
CYR2
CYR2
CYL
7
6
5
7
6
5
VER
VER
VER
V
TODIS
FSPDIS
CC
OOL
R2T
LT
D2
D1
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
15
14
13
7
6
5
15
14
13
7
6
5
15
14
13
Byte
7
6
5
Byte
15
14
13
BHVR
BHVR
BHVR
BHVR
BHVR
BHVR
BHVR
BHVR
BHVR
RANGE
RANGE
RANGE
RANGE
RANGE
RANGE
RANGE
RANGE
RANGE
MIN3
MIN2
MIN1
EN2
ACOU2
ACOU2
7
6
5
7
6
5
7
6
5
Rev. C | Page 34 of 52
Bit
4
Bi
t 3
Bit
2
Bit
1
6
5
4
3
6
5
4
3
6
5
4
3
6
5
4
3
6
5
4
3
4
3
2
1
12
11
10
9
4
3
2
1
12
11
10
9
4
3
2
1
12
11
10
9
4
3
2
1
12
11
10
9
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
PHTR
2
PHTL
PHTR1
V
RE
CC
CYL
CYL
CYR1
CYR1
4
3
2
1
4
3
2
1
VER
STP
STP
STP
RES
FSPD
RDY
LOCK
R1T
RES
V
RES
CC
FAN3
FAN2
FAN1
OVT
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
12
11
10
9
4
3
2
1
12
11
10
9
4
3
2
1
12
11
10
9
4
3
2
1
12
11
10
9
INV
SLOW
SPIN
SPIN
INV
SLOW
SPIN
SPIN
INV
SLOW
SPIN
SPIN
RANGE
THRM
FREQ
FREQ
RANGE
THRM
FREQ
FREQ
RANGE
THRM
FREQ
FREQ
SYNC
EN1
ACOU
ACOU
ACOU2
EN3
ACOU3
ACOU3
4
3
2
1
4
3
2
1
4
3
2
1
Bit
0
Defau
lt
2
0x00
2
0x00
2
0x80
2
0x80
2
0x80
0
0x00
8
0x00
0
0x00
8
0x00
0
0x00
8
0x00
0
0x00
8
0x00
0
0xFF
0
0xFF
0
0xFF
0
0x64
0
0x64
0
0x64
S
CYR2
0x00
CYR1
0x00
0
0x27
0
0x41
STP
0x62 or
0x6A
STRT
0x00
2.5V
0x00
RES
0x00
0
0x00
0
0xFF
0
0x00
0
0xFF
0
0x81
0
0x7F
0
0x81
0
0x7F
0
0x81
0
0x7F
0
0xFF
8
0xFF
0
0xFF
8
0xFF
0
0xFF
8
0xFF
0
0xFF
8
0xFF
SPIN
0x62
SPIN
0x62
SPIN
0x62
FREQ
0xC4
FREQ
0xC4
FREQ
0xC4
ACOU
0x00
ACOU3
0x00
0
0x80
0
0x80
0
0x80
Lock
able?
YES
Y
ES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
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