Analog Devices ADT7460 Manual page 44

ADT7460
Table 60. Register 0x63— Enhance Acoustics Register 2 (Power-On Default = 0x00)
Bit Name R/W
<2:0> ACOU3 Read/Write
<3> EN3 Read/Write
<6:4> ACOU2 Read/Write
<7> EN2 Read/Write
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no
effect.
Table 61. PWM Min Duty Cycle Registers
Register Address
0x64
0x65
0x66
These registers become read-only when the ADT7460 is in automatic fan control mode.
Table 62. PWM Min Duty Cycle Register Bits
Bit Name
<7:0> PWM Duty Cy cle
Description
Th ese bits sele ct the ramp r
its newly calcu lated speed,
en hances the a coustics of t
Time Slot Increase
000 = 1
001 = 2
010 = 3
011 = 5
100 = 8
101 = 12
110 = 24
111 = 48
When this bit is 1, acoustic
T hese bits sele ct the ramp
it s newly calcula ted speed
e nhances the acoustics of
Time Slot Increase
000 = 1
001 = 2
010 = 3
011 = 5
100 = 8
101 = 12
110 = 24
111 = 48
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
R/W Description
Read/Write PWM1 Min Duty Cycle
Read/Write PWM2 Min Duty Cycle
Read/Write PWM3 Min Duty Cycle
Read/Wr ite Descript ion
Read /Wri te These bits define th
0x00 = 0% Duty
0x40 = 25
0x80 = 50% Duty Cycle
0x FF = 1
ate applied to the PWM3 out
PWM3 ramps gracefully at the rate determin
he fan being driven by the PWM3 output.
Time for 33% to 100%
35 s
17.6 s
11.8 s
7 s
4.4 s
3 s
1.6 s
0.8 s
enhancement is enabled on PWM3 outpu
rate applied to the PWM 2 output. Instead
, PWM2 ramps grace fully at the rate determ
the fans being driven by the PWM2 outpu
Time for 33% to 100%
35 s
17.6 s
11.8 s
7 s
4.4 s
3 s
1.6 s
0.8 s
Power-On Default
0x80 (50% duty cycle)
0x80 (50% duty cycle)
0x80 (50% duty cycle)
e PWM duty cycle for PWMx.
MIN
Cyc le (Fan Off)
% Duty Cy cle
00% Duty C ycle (Fan Full Speed)
Rev. C | Page 44 of 52
put. Instead of PWM3 jumpin
ed by these b
t.
of PWM2 jump ing instantaneously to
ined by these bits. This effect
t.
g instantaneously to
its. This effect