Updated Ordering - Analog Devices ADT7460 Manual

ADT7460
1, 2, 3
Parameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM)
Input High Voltage, V
IH
Input Low Voltage, V
IL
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
6
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
R
SCL, SDA Fall Time, t
F
Data Setup Time, t
SU;DAT
Detect Clock Low Timeout, t
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Logic inputs accept input high voltages up to V
3 Timing specifications are tested at logic levels of V
4
Typicals are at T = 25°C and represent the most likely parametric norm.
A
5
The delay is the time between the round robin finishing one set of measurements and starting the next.
6 Guaranteed by design, not production tested.
SCL
t
HD; STA
SDA
t
BUF
P S
TIMEOUT
even when the device is operating down to V
MAX
= 0.8 V for a falling edge and at V
IL
t t
R F
t
LOW
t
HIGH
t t
HD; DAT
Figure 2. Serial Bus Timing Diagram
4
Min Typ Max
2.0
5.5
+0.8
−0.3
0.5
1.7
0.8
−1
+1
5
400
50
1.3
0.6
0.6
1.3
0.6
300
300
100
15 35
.
MIN
= 2.0 V for a rising edge.
IH
t
SU; STA
SU; DAT
S
Rev. C | Page 4 of 52
Unit Test Conditions/Comments
V
V Maximum input voltage
V
V Minimum input voltage
V p-p
V
V
µA V = V
IN CC
µA V = 0
IN
pF
kHz See Figure 2
ns
µs See Figure 2
µs See Figure 2
µs See Figure 2
µs See Figure 2
µs See Figure 2
ns See Figure 2
µs See Figure 2
ns See Figure 2
ms Can be optionally disabled
t
HD; STA
t
SU; STO
P