Memory System - HP Visualize J200 Reference Manual

Memory System

Major features of the design are:
High–performance design (low latency, high bandwidth)
36–bit Real Addresses (32GB)
Supports 4Mbit, 16Mbit and 64Mbit DRAM Technology
Supports 4GB of Memory with 64Mbit DRAMs, 1GB of memory with 16Mbit DRAMs
Minimum memory increment of 32MB (4Mbit DRAM technology, x4 DRAMs, 2 banks of
memory on 2 SIMMs)
Coherent I/O
Multi–Client support via snoop coherency and Interconnect Bus
32 Byte cache lines
Memory Interleaving: 4–way per slave, maximum of 16–way interleaving
Single bit error correct, double bit error detect, single DRAM failure detected for x4 and x8 parts
Address included in ECC encode/decode to aid in hardware characterization and debugging
Memory test and initialization for 2 GB of memory in less than 5 minutes
Hardware Memory Scrubbing is not implemented
16 and 32 byte direct write access to memory. For smaller size writes, clients must read a line,
modify it, and write it back
IEEE 1149.1 boundary scan in all VLSI parts
The memory system uses multiple, independently controlled, sequentially interleaved, banks of Fast
Page Mode DRAM memory to produce up to 768 MB per second (960 MB per second with EDO DRAM)
of maximum data throughput. Multiple memory banks cycle at a rate of 12 MHz (15 MHz for EDO) per
32 bytes of data, on 2 independent DRAM Data buses.
The J Class memory system uses conventional, asynchronous, DRAM technology in the memory design
because of its volume availability, low cost, and large capacity characteristics. The memory system
design supports FPM (Fast Page Mode) DRAM, as well as having the potential for greater performance
through the use of EDO (Extended Data Out) DRAM when supplier uncertainty can be resolved.
SDRAM technology was not considered an alternative due to the uncertainty surrounding its definition
and availability at design time.
Most of the operation references in this section are for the Fast Page Mode design. The EDO
configuration is capable of higher bank throughput than the Fast Page Mode. The EDO bank cycles in 4
clocks (at 60 MHz), while the FPM bank cycles in 5 clocks. Future EDO enhancements are possible,
especially in the 16 Mbit and 64 Mbit generations, depending on DRAM availability.
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