HP Visualize J200 Reference Manual page 29

different system applications.The Central Processing Unit for the PA7200 Module family is the PA7200
CPU chip, which is an evolution of the high–performance single chip superscalar PA7100 CPU design.
The PA7200 implements the 3rd edition of the PA–RISC 1.1 Architecture, documented in the PA–RISC
1.1 Architecture and Instruction Set Reference Manual. This latest design implements a number of design
improvements that increase system performance for both technical and commercial applications
including increased frequency, instruction and data cache prefetching, enhanced superscalar execution,
and enhanced multiprocessor support. The PA7200 connects directly to a new split transaction, 768
Megabytes/second multiprocessor memory and I/O bus. This enables high performance multiprocessor
systems without requiring additional processor interface components, further improving the
price/performance of a PA7200 based system. The PA7200 CPU chip is fabricated in HP's proprietary
CMOS14 technology which features 0.55 micron devices with three levels of metal interconnect
packaged in a 540–pin PGA.