HP Visualize J200 Reference Manual page 65

Figure 4–5 shows the converter's address space as seen by the CPU.
CPU Address Space
$FFBF FFFF
$FD00 0000
$FCFF FFFF
$FC50 0000
$FC4F F000
$FC10 0000
$FC0F FFFF
$FC08 0000
$FC07 FFFF
$FC02 0000
$FC01 F000
$FC01 E001
$FC01 2001
$FC01 1001
$FC01 0001
$FC00 FFFF
$FC00 0000
Control
Address Map
(1024 entries)
address scrambling
IRQ Acknowledge
Status Reg.
Bus Concurrency Reg.
FIFO Enable Reg.
Lock Control Reg.
Accesses from the CPU
Figure 4–5.
(E)ISA I/O (E)ISA Memory
inaccessible
32-Address Bit
24-Address Bit
inaccessible
20-Address Bit
inaccessible
$FFFF
EISA / ISA I/O
$0000
to
$FFFF FFF
$03C0 000
$03BF FFF
EISA
Memory
$0100 000
$00FF FFF
ISA
Memory
$0050 000
$004F FFF
$0010 000
$000F FFF
ISA
Memory
$0008 000
$0007 FFF
$0000 000