HP Visualize J200 Reference Manual page 59

Table 4–2 shows a parallel DMA register map.
Address
*
drst+000
**
dma+000
dma+001
dma+008
dma+00A
dma+00B
dma+00C
dma+00D
dma+00E
dma+00F
dma+010
dma+087
dma+401
dma+40A
dma+487
The J Class Parallel Port DMA controller transfers data from memory to the parallel port without
disturbing the CPU until the transfer sequence is complete. To start a sequence, the DMA channel needs
to have a beginning address and byte count placed into the proper registers. Given that the mode (read or
write) is set up properly, DMA will start once the mask bit is reset. After the sequence is complete, an
interrupt will happen, the mask bit will be set, and the address and count registers will be at their final
value. This controller does not support chaining, so after each sequence the count and address registers
need to be reinitialized to their starting values.
The DMA controller does transactions by arbitrating for the bus, reading one 32-bit word, giving up the
bus, and then handshaking each needed byte out to the parallel device. The DMA controller never
produces multi–word GSC transactions or writes to memory.
Table 4–2. Parallel DMA Register Map
DMA Controller Register Map
Type Size
(Bytes)
write only 1
read/write 1
read/write 1
read only 1
write only 1
write only 1
write only 1
write only 1
write only 1
read/write 1
read/write 1
read/write 1
read/write 1
read/write 1
read/write 1
Description
DMA Reset Register
Current Address Register
Current Count register
Status Register
Write single mask bit
Mode register
Clear byte pointer
Master Clear
Clear Mask register
Mask register
FIFO limit register (not used)
Current Address low page register
High Current Count register
Interrupt Pending register
Current Address High Page register