HP Visualize J200 Reference Manual page 44

When a transaction is received by the multibank DRAM Controller, it immediately begins a memory
bank operation. The only circumstances preventing this are a refresh cycle being in progress, or a previous
transaction that has not yet completed for that memory bank. Figure 3–5 depicts the transaction flow
through the multibank DRAM Controller pipeline, showing that maximum throughput can result from
the overlap of multiple memory banks and busses. This 768 MB/second (960 MB/second for EDO
DRAM) rate is possible when transactions can be aligned to idle DRAM banks and available data "slots"
on the DRAM Data busses.
Figure 3–5. Pipelined transaction flow – 768 MB/s (Fast Page Mode DRAM)
Figure 3–5 demonstrates the top–end performance potential of the memory system. Figure 3–6 shows
the counter example of performance when each memory transaction maps to the same DRAM bank
address. In this case, each subsequent transaction must wait for the prior transaction to complete before it
can be issued. These pipeline stalls result in a cycle time that is much greater than the fully pipelined case
shown in Figure 3–5.