HP Visualize J200 Reference Manual page 48

The primary factor determining memory system throughput and latency is the Average Cycle Time
(ACT), or equivalently stated E[S] (average service time), of each transaction. The memory system ACT
reflects the memory bank and bus cycle time, as well as the effect of resource contention on them – which
is a function of the number of banks and busses. The factors used to determine the ACT are:
Bmx – Maximum Bank cycle or Reservation time (10 clks)
B – Number of Interleaved Banks (1, 2, 4, 8, 16, 32)
b – Number of DRAM Data busses (1, 2, 4)
bmx – Maximum DRAM Data bus cycle or "slot" reservation time
(5 clks for FPM; 4 clks for EDO)
bmn – Minimum Memory system cycle time – the MUX Data bus "slot" timing (2 clks)
The average service time, or Average Cycle Time (ACT) per transaction through the memory system, can
be derived from the following:
The above formula reflects resource contention by representing it in terms of numbers of banks and
busses.
With a method stated for determining average memory system cycle time, the behavior of the memory
system, as a function of the number of banks and busses, is plotted. Figure 3–7 shows the bandwidth
range that the memory system is capable of producing for the conditions specified for Fast Page Mode
DRAM. Memory Bank Contention is shown on the vertical axis with respect to clocks per data cycle
(ACT) on the horizontal axis. Bus contention is also plotted on the horizontal axis. The advantage of
increasing memory banks and busses are shown for the conditions stated.
Figure 3–7 shows the data cycle time versus the increasing Fast Page Mode DRAM banks and busses.