HP Visualize J200 Reference Manual page 46

The theoretical maximum bandwidth available from multiple banks is just the sum of the bandwidths
available from each individual bank. Table 3–1 summarizes the maximum DRAM bandwidth as a
function of the number of banks.
Table 3–1. DRAM Bank Bandwidth
Table 3–2. DRAM Bank Bandwidth for EDO DRAMs
Table 3–2 shows the maximum theoretical bandwidth available from a given number of DRAM banks.
The actual bandwidth provided depends on the interleaving algorithm and the access patterns. For
example, although four banks can provide more bandwidth than a 120 MHz bus, performance for some
applications on some systems improves if more banks are added (due to fewer bank collisions).
The J Class memory system performs at its best when the memory reference pattern takes advantage of
the sequential cache line interleave. In essence, strides that place subsequent references on sequential
cache lines will minimize the potential for bank conflicts and maximize the memory system's
throughput. The worst performing reference pattern is one that has a stride equivalent to the number of
memory banks, causing each reference to continually map to one particular bank. Most other patterns fall
into the random, uniform access case shown here. This modest approach to understand the memory
system behavior is simply to help appreciate the effects of increasing the number of memory banks and
busses for certain types of transaction behavior. It is by no means exhaustive.
Several methods exist to more accurately model the behavior and performance of a particular system
design for anticipated workloads. These range from all encompassing trace–driven simulations, to simple
stochastic process, Markov Chain, analytical models. These abstractions of the actual design attempt to
account for the many subtle interactions present amongst the various interconnected components that
otherwise would go unnoticed. Trace driven simulations run workloads derived from actual application
segments on behavioral models representative of the system design. Analytical models however, use
statistical probability queuing models to help understand the behavior and performance of a given design.
Precise system models capable of accurately predicting performance and processing power can be
somewhat complex due to the large number of states generated by the acquisition and release of parallel
system resources for each of the active transactions. These resources include the CPU, containing caches,