Cache Memory - HP Visualize J200 Reference Manual

Cache Memory

General Overview
Cache Organization
The J200 and J210 processor Instruction cache size is 256K bytes. The J210XC processor –Instruction
cache size is 4K bytes to 1M bytes . The constraining factor in implementing a particular cache size is the
availability of SRAM with the correct timing specifications. The key difference between this processor's
cache implementations and that of other HP workstation models, is that the write pulse width has been
shortened to one clock cycle from two. This requirement is necessary due to copy–ins from the
interconnect bus that deliver a double word, compared with Previous Generation Processor bus (Pbus)
that transferred one word at a time.
I–Cache
The I–Cache is a single set associative cache or direct–mapped cache. For the J200 and J210 CPU
module, the instruction cache size is 256KB. For the J210XC CPU module, the instruction cache size is
1Mbyte . The cache for the J200 and J210 is organized as 32K deep by 64 bits. The cache for the J210XC
is organized as 128K deep by 64 bits . The 64 bits constitute a double word instruction fetch providing the
capability of performing dual instructions for clock cycle. To perform instructions simultaneously, the
instructions must be a certain combination. Prior to writing the double word out to cache, the CPU
determines if the instructions can be bundled. If so, the predecoded information is written out to the cache
along with the double word.
The double word in the I–Cache is protected by word parity. In the case of an I–cache parity error, the line
is marked invalid and the CPU must fetch the line from memory. Reads and writes are all done on a double
word basis.
D–Cache
The D–Cache is also a single set associative or direct–mapped cache. Similar to the I–Cache, the J200 and
J210 CPU module has a data cache size of 256KB. The J210XC CPU module has a data cache size of
1Mbyte. The cache for the J200 and J210 is organized as 32K deep by two 32–bit single words; the data
tags are addressed separately. The cache for the J210XC is orgainized as 128K deep by two 32–bit single
words; the data tags are addressed separately. The D–Cache tags have their own address bus (TADH), and
tag bus (DCTH) in order that the tag may be read earlier than the data. The D–Cache also has a double
word read, but for writes each word can be written independently. Separate writes for each word allow the
word to be written without performing the read and modify.
Each word in the D–Cache is parity protected. There is no ECC on the D–Cache. Thus, if there were a
single bit error on a dirty line, the machine must HPMC. If the line is clean then, like in the I–Cache, the
line can be marked invalid and fetched from memory.