HP Visualize J200 Reference Manual page 40

The multibank DRAM controller provides the next level of control in the memory hierarchy, directly
controlling the operation and timing of the DRAMs. Each controller (four are used) – is capable of
supporting four independent, 16–byte wide banks of memory. Each bank of memory is used to assemble a
32–byte cache line using a Fast Page Mode DRAM cycle. This produces a data rate of 12 MHz (15 MHz
using EDO DRAM) per 32–byte cache line, or 384 MB/sec (480 MB/sec using EDO DRAM), per
DRAM Data bus. Each controller is responsible for tracking the progress of other controllers in the
system for the purpose of scheduling the DRAM Data bus and MUX Data bus usage.
The DRAM Data Path MUX is the simplest of the memory components, in that its primary logic function
is to combine two 144–bit DRAM Data paths into a single, 60 MHz, 144–bit MUX Data bus connected
directly to the master memory controller. Additionally, it buffers the DRAM Data busses so that
expansion beyond eight SIMMS may be accommodated. The DRAM data path MUX coalesces SIMM
Data from two DRAM Data busses and transfers it to the master memory controller, 16–bytes at a time, at
a rate of 60 MHz, or the equivalent of 768 MB/sec (960 MB/sec for EDO DRAM).
The SIMM contains 36 DRAMs, 18 per side, with each side forming a 72–bit data word. It contains no
active elements other than the DRAM. Each half is independently controlled by one of the multibank
DRAM controller's four bank controllers through separate Address, RAS, CAS, OE, and W signals.
The design supports from one to 16 independent banks of memory. Each bank consists of a 16–byte wide
array of memory which is accessed using a page–mode cycle to fetch out 32 bytes of data (cache line). The
memory bank depth is a function of the DRAM density and its organization (for example, 16Mbit x 4,
8Mbit x 8).
Multiple, parallel banks of memory are used collectively to produce very high data throughputs. Each
individual bank is capable of producing 192 MB/second (213 MB/second for EDO DRAM). When
combined, the banks can reach as high as 768 MB/second (960 MB/second for EDO DRAM which is the
limit of the memory system). This maximum limit is primarily a function of the bank cycle time, the
MUX Data bus speed – between the Master Memory Controller and the DRAM Data Path MUX (60
MHz, 16 bytes in width), and the rate transactions are issued to the memory bank controller from the
master memory controller (32 byte transactions @ 30 MHz ).
The memory system uses sequential address interleaving, implemented in each memory bank controller,
to reduce the probability of memory bank address and DRAM Data bus contention. As more banks of
memory and more busses are added to the system, the probability of contention, for both banks and
busses, decreases.
Depending on the number of memory SIMMs installed, the number of interleaved banks varies. The
minimum configuration interleaves two banks, while the maximum configuration interleaves 16 banks.
The interleave is a function of the highest power of 2 contained within the number of installed SIMMs. If,
for instance, ten SIMMs are installed, the memory system would partition that memory into eight equal
sections, for an 8–way interleave. Interleaves of two, four, eight, and 16 are supported.