HP Visualize J200 Reference Manual page 32

CPU–Memory–I/O Interconnect
Introduction
J Class workstations support one or two processors and a single U2 I/O adapter (containing two IOAs) on
a single interconnect bus that implements a snoopy coherency protocol. This section summarizes the
major points of the processor–memory–I/O interconnect bus.
Features
The interconnect bus has the following features:
Provides a price/performance competitive bus for 1–4 way (maximum of 2–way on J Class)
multiprocessing, for high–end workstations and mid–range servers
Provides leadership–effective memory latency
Minimizes interface complexity
Spans both technical and commercial markets
Supports cache coherent I/O
Performs multiple outstanding transactions per module, up to 64
Protocol supports maximum frequency for shared bus
Multiple coherency checks in process simultaneously
CPU Module
Figure 2–2.