HP Visualize J200 Reference Manual page 39

Figure 3–2. J Class Memory System
The master memory controller is the primary interface between the interconnect bus, the system
backplane, and the memory array. It helps manage the processor–memory–I/O interconnect bus protocol,
including cache coherency and arbitration, provides the programmatic interface for system memory,
generates and checks memory ECC, provides buffering of memory write and read transactions from the
interconnect bus to the DRAM Controllers, and provides the primary high–speed memory data path to the
interconnect bus. It is implemented in a 432–pin CPGA and operates most of it's internal circuitry at
one–half the interconnect bus frequency – the interconnect bus interface operates at 120 MHz (nominal.)