HP Visualize J200 Reference Manual page 42

Figure 3–3. Memory SIMM Loading Order
Memory Transaction Behavior
The memory system is a large, multistream, pipeline decoupled by queues at critical points. Transactions
are buffered at several points within the Master Memory Controller and the multibank DRAM Controller.
Figure 3–4 shows a diagram of queue positions, as well as idle issue rates and idle latency for each
component in the memory system.