Cache Memory - HP XM600 - Kayak - 128 MB RAM Technical Reference Manual

The "mono-processing" mode has been implemented in order to support
operating systems that rely on the "legacy" interrupt controller 82C59 and
are not aware of I/O APIC controller operation. Refer to
further details.

Cache Memory

There can be two integrated circuits sealed within a single Pentium III
package. One of these contains the Level-2 (L2) cache memory chip; the
other contains the processor, which itself includes Level-1 (L1) cache
memory.
The L1 cache memory has a total capacity of 32KB (16 KB data, 16 KB
instructions). Depending on the model, the L2 cache memory could have a
capacity of 512 KB or i256 KB, and is composed of four-way set-associative
static RAM. Data is stored in lines of 32 bytes (256 bits). Thus two
consecutive 128-bit transfers with the main memory are involved in each
transaction.
The L2 cache is composed of a TagRam and Burst-pipelined Synchronous
Static RAM (BSRAM) memories and is implemented with multiple die.
Transfer rates between the processor's core and L2 cache can be either:
Same as the processor core clock frequency (full speed) for i256 KB and
•
scale with the processor core frequency.
One-half the processor core clock frequency for 512 KB and scale with the
•
processor core frequency.
Both the TagRam and BSRAM receive clocked data directly from the
processor's core.
The processor includes a dedicated L2 cache bus, thus maintaining the dual
independent bus architecture to deliver high bus bandwidth and high
performance.
The amount of cache memory is set by Intel at the time of manufacture, and
cannot be changed.
2 System Board
Host Bus
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