References; Fpga U2 200 Mhz 2.5V Lvds Oscillator - Xilinx ML630 User Manual

Chapter 1: ML630 Board Features and Operation
Table 1-16: FPGA U2 to U79 (CP2103 Bridge) Connections
The bridge device also provides as many as four GPIO signals that can be defined by the
user for status and control information (see
Table 1-17: FPGA U2 to U79 (CP2103 Bridge) User GPIO Connections
A royalty-free software driver named Virtual COM Port (VCP) is available from Silicon
Laboratories. This driver permits the CP2103 USB to UART bridge to appear as a COM
port to the host computer communications application software (for example,
HyperTerminal or TeraTerm). The VCP driver must be installed on the host computer prior
to establishing communications with the ML630 board.

References

More information on the Silicon Labs CP2103 USB-to-UART bridge is available at:
http://www.silabs.com/products/interface/usbtouart/Pages/default.aspx.

FPGA U2 200 MHz 2.5V LVDS Oscillator

Figure 1-2
Oscillator U63, located on the bottom of the board, is connected to FPGA U2 global clock
inputs.
Table 1-18: FPGA U2 LVDS Oscillator U63 Global Clock Connections
References
More information on the SiTime SI9102AI oscillator is available at:
http://www.sitime.com/products/differential-oscillators/sit9102.
24
FPGA U2 Pin FPGA Function
P11 RTS, output
P10 CTS, input
F10 TX, data out
E10 RX, data in
FPGA U2 Pin
L10
M11
D10
E11
callout [30]
Table 1-18 lists FPGA U2 pin connections to the LVDS oscillator U63.
FPGA U2 Pin
AR33
AT33
www.xilinx.com
Net Name
U2_USB_CTS_I
U2_USB_RTS_O
U2_USB_RXD_I
U2_USB_TXD_O
Table 1-17).
Net Name
U2_USB_GPIO_0
U2_USB_GPIO_1
U2_USB_GPIO_2
U2_USB_GPIO_3
Net Name
U2_LVDS_OSC_P
U2_LVDS_OSC_N
U79 Pin U79 Function
22 CTS, input
23 RTS, output
24 RXD, data in
25 TXD, data out
U79 Pin
19
18
17
16
U63 Pin
4
5
ML630 Board User Guide
UG828 (v1.0) September 28, 2011