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Chapter 1: ML630 Board Features and Operation
X-Ref Target - Figure 1-1
Si570
Header
Receptacle
24x6.25
Header
Si570
Receptacle
USB
SystemACE
Detailed Description
Note:
ML630 (pdf) Schematic 0381388. The ML630 board hosts a complicated clocking system and
intricate FPGA-to-FPGA and Interlaken connector connectivity which the schematic helps clarify.
Please refer to the schematic pages associated with the circuitry described in each section of this
detailed description.
Figure 1-2
that is referenced in
Note:
board.
8
FMC (HPC)
10 Pin Debug Port
HX565T
FF1924
12xGTX
SelectIOs
HX565T
FF1924
FMC (HPC)
Figure 1-1: ML630 Board Block Diagram
This section of the user guide is intended to be read in conjunction with reference to the
shows the ML630 board described in this user guide. Each numbered feature
Figure 1-2
is described in the sections that follow.
The image in
Figure 1-2
is for reference only and might not reflect the current revision of the
www.xilinx.com
4*I2C
Programmable
Oscillators
8 in/16 Diff Out
Crosspoint Switch
To
GTX/GTH
12x11.18G(Rx)
12x11.18G(Tx)
12 x 11.18G(Rx)
12 x 11.18G(Tx)
10 Pin Debug Port
UG828 (v1.0) September 28, 2011
1x100 CFP
Receptacle
10x10 SFP+
12-port SMA
10xXFI
2x40GE
Header
OTU4
MLD
SFI 4.2
SFI-S
1x100 CFP
10x10 SFP+
12-port SMA
Receptacle
10xXFI
2x40GE
OTU4
MLD
SFI 4.2
Header
SFI-S
UG828_c1_01_091211
ML630 Board User Guide
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