Fpga U2 User Gpio Header; Fpga U2 Usb To Uart Bridge - Xilinx ML630 User Manual

FPGA U2 User GPIO Header

Figure 1-2
A standard 2 x 6, 100-mil pitch header (J103) brings out six FPGA I/Os for test purposes.
Table 1-14
Table 1-14: FPGA U2 User GPIO Header J103

FPGA U2 USB to UART Bridge

Figure 1-2
Communications between the ML630 board FPGA U2 and a host computer are
accomplished through a USB cable connected to J106. Control is provided by U79, a USB to
UART bridge (Silicon Laboratories CP2103).
signals for the USB connector J106.
Table 1-15: J106 USB Mini-B Connector Pin Assignments and Signals
The CP2103 supports an I/O voltage range of 2.5V on the ML630 board. The connections
between FPGA U2 and CP2103 should use the LVCMOS25 I/O standard. UART IP (for
example, Xilinx® XPS UART Lite) must be implemented in the FPGA logic. FPGA U2
supports the USB to UART bridge using four signal pins:
•
•
•
•
Connections of these signals between the FPGA and the CP2103 at U79 are listed in
Table
ML630 Board User Guide
UG828 (v1.0) September 28, 2011
callout [28]
lists these pins. J103 odd pin numbers are wired to GND (ground).
FPGA U1 Pin Net Name
J35 U2_USER_IO_1
K35 U2_USER_IO_2
D35 U2_USER_IO_3
E35 U2_USER_IO_4
P35 U2_USER_IO_5
P34 U2_USER_IO_6
callout [29]
J106 Pin Signal Name
1 VBUS
2 U2_USB_D_N
3 U2_USB_D_P
4 ID
Transmit (TX)
Receive (RX)
Request to Send (RTS)
Clear to Send (CTS)
1-16.
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J103 Pin
2
4
6
8
10
12
Table 1-15 lists the pin assignments and
Description
+5V from host system
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Not used8
Detailed Description
23