References - Xilinx ML630 User Manual

Chapter 1: ML630 Board Features and Operation
Table 1-7: : J54 USB Mini-B Connector Pin Assignments and Signals (Cont'd)
The CP2103 supports an I/O voltage range of 2.5V on the ML630 board. The connections
between FPGA U1 and CP2103 should use the LVCMOS25 I/O standard. UART IP (for
example, Xilinx® XPS UART Lite) must be implemented in the FPGA logic. FPGA U1
supports the USB to UART bridge using four signal pins:
•
•
•
•
Connections of these signals between the FPGA and the CP2103 at U26 are listed in
Table
Table 1-8: FPGA U1 to U26 (CP2103 Bridge) Connections
The bridge device also provides as many as four GPIO signals that can be defined by the
user for status and control information (see
Table 1-9: FPGA U1 to U26 (CP2103 Bridge) User GPIO Connections
A royalty-free software driver named Virtual COM Port (VCP) is available from Silicon
Laboratories. This driver permits the CP2103 USB to UART bridge to appear as a COM
port to the host computer communications application software (for example,
HyperTerminal or TeraTerm). The VCP driver must be installed on the host computer prior
to establishing communications with the ML630 board.

References

More information on the Silicon Labs CP2103 USB-to-UART bridge is available at:
http://www.silabs.com/products/interface/usbtouart/Pages/default.aspx.
20
J54 Pin Signal Name
3 U1_USB_D_P
4
Transmit (TX)
Receive (RX)
Request to Send (RTS)
Clear to Send (CTS)
1-8.
FPGA U1 Pin FPGA Function
P11 RTS, output
P10 CTS, input
P10 TX, data out
E10 RX, data in
FPGA U1 Pin
L10
M11
D10
E11
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Bidirectional differential serial data (P-side)
ID Not used
Net Name
U1_USB_CTS_I
U1_USB_RTS_O
U1_USB_RXD_I
U1_USB_TXD_O
Table 1-9).
Net Name
U1_USB_GPIO_0
U1_USB_GPIO_1
U1_USB_GPIO_2
U1_USB_GPIO_3
Description
U26 Pin U26 Function
22 CTS, input
23 RTS, output
24 RXD, data in
25 TXD, data out
U26 Pin
19
18
17
16
ML630 Board User Guide
UG828 (v1.0) September 28, 2011