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cPCI-MXS64 Technical Reference Manual
TIME-OUT
The programmable watchdog has two stages: the first stage has a variable time-out while
the second stage has a fixed one.
The first stage time-out is chosen at runtime from eight preset values (see table below). The
first stage time-out generates an NMI interrupt (if enabled in register n92h). An appropriate
NMI handler must be written, otherwise this will be treated as a parity error by the default
BIOS NMI handler; see register n92h description for a suggestion on how to do this.
The second stage times-out 8.6ms ±10% (depending on the temperature) after the first one
and generates a master reset.
A reset from the programmable watchdog is latched for reset source identification; see
reset history description in Section 4.3.
3.3.4.3.
Thermal Management
The thermal management is built around two digital temperature sensors and a thermal
watchdog. Both devices can be programmed to set their outputs when the temperature of
the processor or the ambient temperature exceeds a programmable high limit, and reset its
output when the temperature is under a programmable low limit. A special routine is
implemented to throttle the CPU clock until the temperature falls below the programmed
low limit.
Please refer to Section 4.1.10 CPU/Board Features Setup– Thermal Management Options
for a complete information on thermal management setups.
WDS[2,0]
NMI Timeout
000
001
010
011
100
101
110
111
RESET Timeout
0.016s
0.065s
0.261s
1.044s
4.174s
16.69s
66.79s
267.1s
3-22
0.016s + 1ms
0.065s + 1ms
0.261s + 1ms
1.044s + 1ms
4.174s + 1ms
16.69s + 1ms
66.79s + 1ms
267.1s + 1ms
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