Peripheral Characteristics - Texas Instruments SimpleLink CC2652PSIP Manual

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8.15 Peripheral Characteristics

8.15.1 ADC
Analog-to-Digital Converter (ADC) Characteristics
T = 25 °C, V = 3.0 V and voltage scaling enabled, unless otherwise noted.
c DDS
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
Input voltage range
Resolution
Sample Rate
Offset
Gain error
(4)
DNL Differential nonlinearity
INL Integral nonlinearity
ENOB Effective number of bits
THD Total harmonic distortion
Signal-to-noise
SINAD,
and
SNDR
distortion ratio
SFDR Spurious-free dynamic range
Conversion time
Current consumption
Current consumption
Reference voltage
Reference voltage
Reference voltage
Reference voltage
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TEST CONDITIONS
Internal 4.3 V equivalent reference
Internal 4.3 V equivalent reference
Internal 4.3 V equivalent reference
9.6 kHz input tone
Internal 4.3 V equivalent reference
9.6 kHz input tone, DC/DC enabled
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal reference, voltage scaling disabled,
14-bit mode, 200 kSamples/s, 600 Hz input tone
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 150 Hz input tone
Internal 4.3 V equivalent reference
9.6 kHz input tone
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal 4.3 V equivalent reference
9.6 kHz input tone
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal 4.3 V equivalent reference
9.6 kHz input tone
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Serial conversion, time-to-output, 24 MHz clock
Internal 4.3 V equivalent reference
VDDS as reference
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include the gain/
offset compensation factors stored in FCFG1
Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TI-RTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
V = 4.3 V × 1408 / 4095
ref
VDDS as reference, input voltage scaling enabled
VDDS as reference, input voltage scaling disabled
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SWRS263A – FEBRUARY 2021 – REVISED JUNE 2022
(1)
(2)
(2)
(2)
, 200 kSamples/s,
(2)
, 200 kSamples/s,
(5)
(5)
(2)
, 200 kSamples/s,
(2)
, 200 kSamples/s,
(2)
, 200 kSamples/s,
(2)
CC2652PSIP
CC2652PSIP
MIN TYP MAX
0 VDDS
12
200
–0.24
7.14
>–1
±4
9.8
9.8
10.1
11.1
11.3
11.6
–65
–70
–72
60
63
68
70
73
75
50 Clock Cycles
0.42
0.6
(2) (3)
4.3
1.48
VDDS
VDDS /
(3)
2.82
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UNIT
V
Bits
ksps
LSB
LSB
LSB
LSB
Bits
dB
dB
dB
mA
mA
V
V
V
V
23