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6 Detailed Description
6.1
Functional Block Diagram
Figure 6-1
shows the functional block diagram.
MUX
RX_IN1
RX_IN2
VDD_PA
TX_OUT
Analog Front End
VSS_PA
EN
EN2
Digital Control
State Machine
ASK/OOK
MOD
OSC_IN
Crystal or Oscillator
Timing System
OSC_OUT
6.2
Power Supplies
The TRF7962A positive supply input VIN (pin 2) sources three internal regulators with output voltages
VDD_RF, VDD_A, and VDD_X. All regulators require external bypass capacitors for supply noise filtering
and must be connected as indicated in reference schematics. These regulators provide a high power
supply reject ratio (PSRR) as required for RFID reader systems. All regulators are supplied by VIN (pin 2).
The regulators are not independent and have common control bits in register 0x0B for output voltage
setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B, bit
7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest
possible supply voltage for RF output (to ensure maximum RF power output). The manual mode lets the
user manually configure the regulator settings.
Copyright © 2011–2020, Texas Instruments Incorporated
Phase and
Gain
Amplitude
Detector
RSSI
(External)
Phase and
Gain
Amplitude
Detector
ISO
Protocol
Handling
Transmitter
Conversion
CRC and Parity
Figure 6-1. Functional Block Diagram
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SLOS757G – DECEMBER 2011 – REVISED MARCH 2020
RSSI
(AUX)
(Control
Registers and
Command
RSSI
(Main)
Filter
Digitizer
and AGC
Interface
Decoder
Bit
Framing
Framing
Serial
Voltage Supply Regulator Systems
(Supply Regulators and Reference Voltages)
Copyright © 2017, Texas Instruments Incorporated
TRF7962A
VDD_I/O
I/O_0
Logic
State
I/O_1
Control
Logic
I/O_2
I/O_3
I/O_4
Logic)
I/O_5
I/O_6
MCU
I/O_7
IRQ
SYS_CLK
12-Byte
FIFO
DATA_CLK
VIN
VDD_A
BAND_GAP
VSS_A
VDD_RF
VSS_RF
VDD_X
VSS
VSS_D
Detailed Description
TRF7962A
11
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