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M306H7T3-RPD-E User's Manual
Notes on Maskable Interrupts:
Even if a user program is not being executed (including when run-time debugging is being performed),
the evaluation MCU keeps running so as to control the emulation pod. If a maskable interrupt is
requested when the user program is not being executed (including when run-time debugging is being
performed), the maskable interrupt request cannot be accepted, because the emulator disables interrupts.
The interrupt request is accepted immediately after the user program execution is started.
Take note that when the user program is not being executed (including when run-time debugging is
being performed), a peripheral I/O interruption is not accepted.
Note on DMA Transfer:
With this product, the program is stopped with a loop program to a specific address. Therefore, if a
DMA request is generated while the program is stopped, a DMA transfer is executed, but it may not be
performed correctly. Also note that the below registers have been changed to generate a DMA transfer
as explained here even when the program is stopped.
DMA0 transfer counter registers : TCR0
DMA1 transfer counter registers : TCR1
Note on Pullup Control:
With this product, ports P0 to P5 are not pulled up by the pullup control register. To pull up the ports P0
to P5, mount the included network resistor (51 kΩ) to the inside of the emulator as occasion demands.
How to mount it, refer to "2.9.5 Installing and Removing Network Resistors for Pullup" (page 45).
*Note: Ports P6 to P9 are pulled up by the pullup control registers.
*Note: Pullup control registers themselves can be read and written into properly.
Note on Setting "1" to Protect Bit 2 (PCR2) with Sub Clock:
When the CPU clock is set to the sub-clock (low-speed mode or low power dissipation mode), even if
you enable the PRC2 bit, writing to the register protected by the PRC2 bit (PD9, S3C and S4C
registers) cannot be done properly. When you enable the PRC2 bit and write to the register protected by
the PRC2 (PD9, S3C and S4C registers), do not set the CPU clock to the sub-clock.
Notes on Setting "1" to Protect Bit 2 (PRC2) in Division by 2 Mode:
Under the following conditions, even if you enable the PRC2 bit, writing to the register protected by the
PRC2 bit (PD9, S3C and S4C registers) cannot be done properly.
(1) Between when stop mode is released and when a hardware reset is executed
(2) Between when low power dissipation mode is enabled and when a hardware reset is executed
Therefore, if the condition (1) or (2) applies, when you enable the PRC2 bit and write to the register
protected by the PRC2 (PD9, S3C and S4C registers), set the CPU clock neither to the main clock in
division by 2 mode nor to the on-chip oscillator clock in division by 2 mode.
Note on the Input Thresholds for the Pins P1_5/INT3, P1_6/INT4 and P1_7/INT5
With this product, regarding pins P1_5/INT3, P1_6/INT4 and P1_7/INT5, a device which port or data
bus inputs to and a device which INT interrupt inputs to are different as follows:
Device which port or data bus inputs to: Port emulation FPGA (input level: TTL)
Device which INT interrupt inputs to: Evaluation MCU for emulating peripheral functions (input
level: CMOS Schmidt)
Therefore, the port input level can be read as "H" immediately after an INT interrupt (falling), and the
port input level can be read as "H" immediately before an INT interrupt (rising).
Note on Final Evaluation:
Be sure to evaluate your system with an evaluation MCU. Before starting mask production, evaluate
your system and make final confirmation with a CS (Commercial Sample) version MCU.
REJ10J0964-0100 Rev.1.00 August 01, 2005
IMPORTANT
4. Hardware Specifications
Page 71 of 88
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