Seco SBC ADLER User Manual page 49

4.3.15 LVDS Configuration submenu
Menu Item Options
LVDS interface Enabled / Disabled
Edid Mode External / Default / Custom
640x480 / 800x480 / 800x600 /
1024x600 / 1024x768 / 1280x720 /
EDID 1280x800 / 1280x1024 / 1366x768 /
1400x900 / 1600x900 / 1680x1050 /
1920x1080
Color Mode VESA 24bpp / JEIDA 24bpp / 18 bpp
Interface Single Channel / Dual Channel
Active High
DE Polarity
Active Low
V-Sync Polarity Negative / Positive
H-Sync Polarity Negative / Positive
LVDS Advanced Options See Submenu
Save to EEPROM Enabled / Disabled
4.3.15.1
LVDS Advanced options submenu
Menu Item Options
No Spreading / 0.5% / 1.0% / 1.5% /
Spreading Depth
2.0% / 2.5%
150 mV / 200 mV / 250 mV / 300 mV
Output Swing
/ 350 mV / 400 mV / 450 mV
T3 Timing 0 ÷ 255
T4 Timing 0 ÷ 255
T12 Timing 0 ÷ 255
T2 Delay Enabled / Disabled
ADLER
ADLER User Manual - Rev. First Edition: 1.0 - Last Edition: 1.2 - Author: A.R./S.B. - Reviewed by M.B. Copyright © 2022 SECO S.p.A.
Description
Enables or Disables the LVDS interface. When enabled all the following parameters will appear
Select the source (EDID, Extended Display Identification Data) to be used for the internal flat panel.
Depending on the setting chosen, only some of the following option or none will appear.
Only available when Edid Mode is set to "default". Select a software resolution (EDID settings) to be used
for the internal flat panel.
Select the color depth of LVDS interface. For 24-bit color depth, it is possible to choose also the color
mapping on LVDS channels, i.e. if it must be VESA-compatible or JEIDA compatible.
Allows configuration of LVDS interface in Single or Dual channel mode
Data Enable Polarity
Vertical Sync Signal Polarity: Default is Negative (Active Low)
Horizontal Sync Signal Polarity: Default is Negative (Active Low)
LVDS Advanced Options Configurations
Save current LVDS configuration to module EEPROM
Description
Sets spread-spectrum bandwidth of LVDS clock frequency for EMI reduction
Sets the LVDS differential output swing level
Minimum T3 timing of panel power sequence to enforce (expressed in units of 50ms)
Minimum T4 timing of panel power sequence to enforce (expressed in units of 50ms)
Minimum T12 timing of panel power sequence to enforce (expressed in units of 50ms.
When Enabled, T2 is delayed by 20ms ± 50%
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