Video Interface; Configuration; Video Bios Selection; Svga Output Connector - VersaLogic Python EBX-11 Reference Manual

Video Interface

An on-board video controller integrated into the chipset provides high performance video output
for the EBX-11.
C
ONFIGURATION
The video interface uses PCI interrupt INTA*. CMOS Setup is used to select the IRQ line routed
to INTA*.
The EBX-11 uses shared memory architecture. This allows the video controller to use variable
amounts of system DRAM for video RAM. The amount of RAM used for video is set with a
CMOS Setup option.
The EBX-11 supports two types of video output, SVGA and LVDS Flat Panel Display. A CMOS
Setup option is used to select which output is enabled after POST.
V BIOS S
IDEO ELECTION
Jumper V2[5-6] can be removed to allow the system to boot off of the Secondary Video BIOS.
Unlike the Primary Video BIOS, the Secondary Video BIOS can be reprogrammed in the field.
SVGA O C
UTPUT
See the diagram on page 16 for the location of connector J6. An adapter cable, part number CBR-
1201, is available to translate J6 into a standard 15-pin D-Sub SVGA connector.
This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
EBX-11 Reference manual
ONNECTOR
Table 17: Video Output Pinout
J6 Signal
Pin Name Function
1 GND Ground
2 RED Red video
3 GND Ground
4 GREEN Green video
5 GND Ground
6 BLU Blue video
7 GND Ground
8 HSYNC Horizontal sync
9 GND Ground
10 VSYNC Vertical sync
11 CRT_SCL DDC data clock line
12 CRT_SDA DDC serial data line
Interfaces and Connectors
Mini DB15
Pin
6
1
7
2
8
3
5
13
10
14
15
12
39