VersaLogic Python EBX-11 Reference Manual page 73

SPICON2 (READ/WRITE) 1D9h
D15
INT1 Reserved
Bit Mnemonic
D15 INT1
–
D14
D13-D12 SPISET
–
D11
D10 DONE
D9 CI
–
D8
EBX-11 Reference manual
D14 D13 D12
SPISET1 SPISET0
Table 37: SPI Control Register 2 Bit assignments
Description
SPI Hardware Interrupt Enable – Setting this bit enables SPI devices with a
hardware interrupt feature to generate an interrupt request.
0 = SPI device interrupts disabled
1 = SPI device interrupts enabled
This IRQ is shared among all SPI devices on-board and connected to the
EBX-11.
Reserved – This bit is unused and read as 1.
SPI Frame Length Control – These bits set the SPI cycle frame length.
SPISET1 SPISET0
0 0
0 1
1 0
1 1
Reserved – This bit is unused and read as 1.
SPI Cycle Complete Flag – Set by hardware on completion of every SPI bus
transaction. Cleared by writing a 0 to this bit or by hardware on initiation of a
new SPI transaction.
SPI Clock Idle – CI along with CP in SPICON1 combine to set the SCLK
behavior.
CI CP SCLK
1 0 Idle low, rising edge active
1 1 Idle low, falling edge active
0 1 Idle high, rising edge active
0 0 Idle high, falling edge active
Reserved – This bit is unused and read as 1.
D11 D10
Reserved DONE
Frame Length
8 Bit
16 Bit
Invalid
24 Bit
Legacy SPI Interface
D9 D8
CI Reserved
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