Video Interface (J11); Configuration; Lvds Flat Panel Display Connector - VersaLogic Tiger Reference Manual

Video Interface (J11)

An on-board video controller integrated into the chipset provides high-performance LVDS video
output for the VL-EPM-24. The VL-EPM-24 can also be operated with a VGA monitor through
an adapter.
C
ONFIGURATION
The VL-EPM-24 uses a shared-memory architecture. This allows the video controller to use 256
MB of system DRAM for video RAM.
LVDS F P
LAT ANEL
The integrated LVDS flat panel display in the VL-EPM-24 is an ANSI/TIA/EIA-644-1995
specification-compliant interface. It can support up to 24 bits of RGB pixel data plus three bits of
timing control (HSYNC/VSYNC/DE) on the four differential data output pairs. The LVDS clock
frequency ranges from 25 MHz to 112 MHz.
VL-EPM-24 Reference Manual
D C
ISPLAY ONNECTOR
Table 6: LVDS Flat Panel Display Pinout
J11 Signal
Pin Name
1 GND
2 NC
3 LVDSA3
4 LVDSA3#
5 GND
6 LVFSCLK0
7 LVDSCLK0#
8 GND
9 LVDSA2
10 LVDSA2#
11 GND
12 LVDSA1
13 LVDSA1#
14 GND
15 LVDSA0
16 LVDSA0#
17 GND
18 GND
19 +3.3V
20 +3.3V
Function
Ground
No Connection
Diff. Data 3 (+)
Diff. Data 3 (–)
Ground
Differential Clock (+)
Differential Clock (–)
Ground
Diff. Data 2 (+)
Diff. Data 2 (–)
Ground
Diff. Data 1 (+)
Diff. Data 1 (–)
Ground
Diff. Data 0 (+)
Diff. Data 0 (–)
Ground
Ground
Protected Power Supply
Protected Power Supply
Interfaces and Connectors
27