VersaLogic Python EBX-11 Reference Manual page 72

SPICON1 (READ/WRITE) 1D8h
D7
INT0 BUSY
Bit Mnemonic
D7 INT0
D6 BUSY
D5 CP
D4-D3 CLK1-CLK0
D2-D0 CS2-CS0
EBX-11 Reference manual
D6 D5 D4
CP CLK1
Table 36: SPI Control Register 1 Bit Assignments
Description
SPI Interrupt on Completion Enable – Setting this bit enables the SPI
controller to generate an interrupt on completion of every SPI transaction.
0 = SPI interrupts disabled
1 = SPI interrupts enabled
This IRQ is shared among all SPI devices on-board and connected to the
EBX-11.
SPI Busy Flag – Set by hardware on the start of every SPI bus transaction
and cleared upon completion of a new transaction.
0 = Transaction complete
1 = Transaction in progress
Note: This bit is read-only.
SPI Master Clock Polarity – CP along with CI in SPICON2 combine to set the
SCLK behavior.
CI CP SCLK
1 0 Idle low, rising edge active
1 1 Idle low, falling edge active
0 1 Idle high, rising edge active
0 0 Idle high, falling edge active
SPI Master Clock Frequency – These bits set the SPI Master clock
frequency.
CLK1 CLK0 Frequency
0 0
1 0
0 1
1 1
SPI Master Chip Select – These bits select which of the EBX-11's seven chip
selects will be asserted during an SPI transaction.
CS2 CS1 CS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
D3 D2
CLK0 CS2
1MHz
2MHz
4MHz
8MHz
Chip Select
None, port disabled
External Chip Select 0
External Chip Select 1
External Chip Select 2
External Chip Select 3
On-Board A/D Converter Chip Select
On-Board Digital I/O Chip Select Chan 0-15
On-Board Digital I/O Chip Select Chan 16-31
Legacy SPI Interface
D1 D0
CS1 CS0
66