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Related Manuals for VersaLogic Fox VL-EPM-19
Summary of Contents for VersaLogic Fox VL-EPM-19
- Page 1 Programmer’s Reference Manual REV. April 2019 (VL-EPM-19) DMP Vortex86DX2 SoC-based SBC with dual Ethernet, Video, USB, SATA, Counter/Timers, Mini PCIe, microSD, GPIO, SPX, and PC/104-Plus Interface...
- Page 2 Copyright © 2015-2019 VersaLogic Corp. All rights reserved. Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
- Page 3 Utility routines and benchmark software This is a private page for EPM-19 users that can be accessed only be entering this address directly. It cannot be reached from the VersaLogic homepage. The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with your VersaLogic product.
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Page 4: Table Of Contents
Contents Introduction ........................1 Related Documents ......................1 System Resources and Maps ..................2 Memory Map ........................2 IRQ Map ..........................2 I/O Map ..........................3 FPGA Registers ......................4 Accessing the FPGA ......................4 FPGA I/O Space ......................... 4 FPGA Register Map ...................... - Page 5 Contents Table 2: IRQ Map ....................... 2 Table 3: I/O Map ......................... 3 Table 4: FPGA I/O Map ...................... 4 Table 5: FPGA Register Map....................5 Table 6: PCR – Product Code and LED Register ............... 6 Table 7: PSR – Product Status Register ................6 Table 8: SCR –Status/Control Register ................
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Page 6: Introduction
BIOS Setup utility. All BIOS menus, submenus, and configuration options are described. VersaAPI Installation and Reference Guide – describes the shared library of API calls for reading and controlling on-board devices on certain VersaLogic products. EPM-19 Programmer’s Reference Manual... -
Page 7: System Resources And Maps
System Resources and Maps Memory Map Table 1: Memory Map Address Range Description 00000000 – 0009FFFF System RAM 000A0000 – 000AFFFF EGA/VGA video memory 000B0000 – 000B7FFF MDA RAM, Hercules graphics display RAM 000B8000 – 000BFFFF CGA display RAM 000C0000 – 000C7FFF EGA/VGA BIOS ROM 000C8000 –... -
Page 8: I/O Map
System Resources and Maps I/O Map Table 3: I/O Map I/O Address Range Device/Owner 0000h – 000Fh DMA 8237-1 0020h – 0021h 8259-1 programmable interrupt controller 0022h – 0023h Indirect access registers (6117D configuration port) 002Eh – 002Fh Forward to LPC bus 0040h –... -
Page 9: Fpga Registers
FPGA Registers Accessing the FPGA To access the FPGA, obtain the PCI Base Address Register value (BAR) and add it to the Offset Address provided in Table 5 below. The PCI BAR can be obtained by reading the 32-bit hexadecimal value (indicated by the 0x prefix) loaded in the PCI Configuration register at address 0x10 for PCI Bus 02, Dev 04, Func 00. -
Page 10: Fpga Register Map
FPGA Registers FPGA Register Map Register Access Key Read/Write Read-only (status or reserved) R/WC Read-status/Write-1-to-Clear Write-only (0 if read) RSVD Reserved (registers implemented but not used) Table 5: FPGA Register Map Offset Identifier Address 0x00 PLED EPM-19 PRODUCT_CODE = 0010010 0x01 REV_LEVEL RSVD... -
Page 11: Fpga Register Descriptions
FPGA Registers FPGA Register Descriptions Register Access Key Read/Write Read-only (status or reserved) R/WC Read-status/Write-1-to-Clear Write-only (0 if read) RSVD Reserved (registers implemented but not used) RODUCT NFORMATION EGISTERS The FPGA register at offset 0x00 (PCR VersaReg) provides read access to the product code. At offset 0x01 (PSR VersaReg), the revision level can be read. -
Page 12: Status/Control Register
FPGA Registers TATUS ONTROL EGISTER Table 8: SCR –Status/Control Register Identifier Access Default Description Reserved Reserved. Writes are ignored; reads always return 0. Reserved Reserved. Writes are ignored; reads always return 0. Reserved Reserved. Writes are ignored; reads always return 0. Debug LED (controls the blue LED): DEBUG_LED 0 –... -
Page 13: Spi Control Registers
FPGA Registers SPI C ONTROL EGISTERS This section describes the SPI registers for the EPM-19. In this section, the term “BAR” refers to the PCI Base Address Register value. Refer to the section titled Accessing the FPGA on page 4 for information on determining the values of the BAR and the Offset address. SPICONTROL (Read/Write) BAR + Offset 08h CPOL CPHA... - Page 14 FPGA Registers SPISTATUS (Read/Write) BAR + Offset 09h Reserved Reserved SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY Table 10: SPI Status Register Mnemonic Description D7-D6 Reserved Reserved SPI SCLK Frequency – These bits set the SPI clock frequency. SPICLK1 SPICLK0 Frequency 1.042 MHz D5-D4 SPICLK(1:0)
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Page 15: Spi Data Registers
FPGA Registers SPI D EGISTERS SPIDATA0 (Read/Write) BAR + Offset 0Ah SPIDATA1 (Read/Write) BAR + Offset 0Bh SPIDATA2 (Read/Write) BAR + Offset 0Ch SPIDATA3 (Read/Write) BAR + Offset 0Dh SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this register initiates the SPI clock and, if the MAN_SS bit = 0, also asserts a slave select to begin an SPI bus transaction. -
Page 16: Spi Debug Control Register
FPGA Registers SPI D EBUG ONTROL EGISTER Table 11: SPI – SPI Debug Control Register Identifier Access Default Description Reserved Reserved – Writes are ignored. Reads always return 0 mSATA/PCIe Mux Selection for Minicard Slot (and 2 SATA connector): • 000 –... -
Page 17: Miscellaneous Fpga Registers
FPGA Registers FPGA R ISCELLANEOUS EGISTERS Table 12: MISCR1 – Misc. Control Register #1 Identifier Access Default Description Reserved Reserved. Writes are ignored; reads always return 0. Reserved Reserved. Writes are ignored; reads always return 0. Reserved Reserved. Writes are ignored; reads always return 0. Reserved Reserved. -
Page 18: Gpio Registers
FPGA Registers GPIO R EGISTERS AUXDIR This register controls the direction of the eight GPIO signals. Table 14: AUXDIR – Auxiliary GPIO Direction Control Register Identifier Access Default Description Sets the direction of GPIO_8 DIR_GPIO8 0 – Input 1 – Output Sets the direction of GPIO_7 DIR_GPIO7 0 –... - Page 19 FPGA Registers AUXPOL This register controls the polarity of the eight GPIO signals. Table 15: AUXPOL – Auxiliary GPIO Polarity Control Register Identifier Access Default Description Sets the polarity of GPIO_8 (Note) POL_GPIO8 0 – No polarity inversion 1 – Invert polarity Sets the polarity of GPIO_7 (Note) POL_GPIO7 0 –...
- Page 20 FPGA Registers AUXOUT This register sets the GPIO output value. This value will only set the actual output if the GPIO direction is set as an output. Reading this register does not return the actual input value of the GPIO; use the AUXIN register for that function. This register can be used to detect input/output conflicts.
- Page 21 FPGA Registers AUXIN This register sets the GPIO input value. It reads the input value regardless of the setting on the direction (that is, it always reads the input). This reads the actual state of the GPIO pin into the FPGA.
- Page 22 FPGA Registers AUXIMASK This is the interrupt mask register for the GPIOs and the interrupt enables and selection. Table 18: AUXIMASK – Auxiliary GPIO I/O Interrupt Mask and Control Register Identifier Access Default Description GPIO_8 Interrupt Mask 0 – Interrupt disabled IMASK_GPIO8 1 –...
- Page 23 FPGA Registers AUXISTAT This is the interrupt mask register for the GPIOs and the interrupt enables and selection. Table 19: AUXISTAT– Auxiliary GPIO I/O Interrupt Mask and Status Register Identifier Access Default Description GPIO_8 interrupt status. A read returns the interrupt status. Writing a 1 to this bit clears the R/WC ISTAT_GPIO8 interrupt status.
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Page 24: Com Port Register
FPGA Registers Table 20: AUXIMODE1– Auxiliary GPIO I/O Mode Register Identifier Access Default Description GPIO_8 mode MODE_GPIO8 0 – GPIO (I/O) 1 – Timer 0 input ICTC0 (Input) GPIO_7 mode MODE_GPIO7 0 – GPIO (I/O) 1 – Timer 1 input ICTC1 (Input) GPIO_6 mode MODE_GPIO6 0 –... -
Page 25: Fpga Interrupt Interface
FPGA Registers FPGA Interrupt Interface The FPGA signal FPGA_INT# is an active low interrupt routed to the Vortex86DX2 GPIO pin GP02. The source for this interrupt signal can be from the following FPGA functions: Timer SPX interface The INTRTEST bit in the TISR may be used to test this signal connectivity since there is no SERIRQ availability for this board (because the FPGA interface is PCI based instead of LPC based). -
Page 26: Programming Information For Hardware Interfaces
Programming Information for Hardware Interfaces PC/104 Expansion Bus Seven IRQs have been shown to work with the ISA bus expansion cards. As listed in Table 17, they are IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ10, and IRQ11. There are conflicts with all other IRQ assignments per the Vortex86DX2 resources, and by default IRQ3, IRQ4, IRQ10, and IRQ11 are assigned to the four COM Ports. -
Page 27: Pci Express Ports (Pcie)
Programming Information for Hardware Interfaces PCI Express Ports (PCIe) The Vortex86DX2 SoC supports two PCI Express 1.1 compliant single lane (x1) ports. Internal to the SoC is a PCI-to-PCIe bridge that provides the functionality of transactions occurring between a master on one of the internal PCI busses and a target on one of the two PCIe bus ports. Note that no SoC PCI bus is available on the SoC pins for external use. -
Page 28: Gpio Configuration
Programming Information for Hardware Interfaces GPIO Configuration Table 19 lists the EPM-19 usage of the Vortex86DX2 3.3V muxed GPIO signals. These signals are muxed between many different functional possibilities, so this list displays 8-bit blocks of GPIO port differentiation (for GPIO-P0 through GPIO-PA) with an alternating background fill pattern. - Page 29 Programming Information for Hardware Interfaces Internal or GPIO number/ EPM-19 signal Default External/ Function Signal Use name Value Pull-Up or Down GP44/ Internal/ Serial data in / RX data (COM1, RS-232 UART1_SIN SIN1 input Pull-up only) GP45/ Not used DTR1# output GP46/ Internal/ PD_UART1_...
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Page 30: Industrial I/O Functions And Spi Interface
Programming Information for Hardware Interfaces Internal or GPIO number/ EPM-19 signal Default External/ Function Signal Use name Value Pull-Up or Down GP83/ External/ PD_UART9_ Ring Indicator (tied low) RI9# input Pull-down GP84/ Internal/ Serial data in / RX data (COM2, RS-232 UART9_SIN SIN9 input Pull-up... -
Page 31: Serial Ports
Programming Information for Hardware Interfaces Serial Ports The EPM-19 includes four on-board 16550-based serial channels located at standard PC I/O addresses. Each COM port can be independently enabled or disabled in the BIOS Setup utility. All four COM ports by default are set to RS-232 mode ... -
Page 32: Serial Port Assignment
Programming Information for Hardware Interfaces Table 25: GPIO Port 2 Direction Register – 0x9A Description 0 = Sets pin 7 to input mode 1 = Sets pin 7 to output mode 0 = Sets pin 6 to input mode 1 = Sets pin 6 to output mode 0 = Sets pin 5 to input mode 1 = Sets pin 5 to output mode 0 = Sets pin 4 to input mode... -
Page 33: Com Ports (Fifo Uarts)
Programming Information for Hardware Interfaces COM P (FIFO UART ORTS The EPM-19 supports two RS232 8-wire COM ports and two multiprotocol (RS-232/422/485) 4- wire COM ports. The COM ports are 16C550 compatible with default internal pull-ups, a programmable baud rate generator with the data rate from 2400 bps to 115,200 bps (standard baud rates, 115,200 bps is default), and also high-speed settings from 31,200 bps to 748,800 bps (only useful for COM3 and COM4 in RS-422 or RS-485 modes). - Page 34 Programming Information for Hardware Interfaces Table 28: COM Port PCI Address Map Four-bit value of PCI Address for UART#/COM# UART I/O Address IRQ select 32-bit register UART1/COM1 0x03F8 0x4 = IRQ4 0x54 UART2/COM3 0x03E8 0x2 = IRQ3 0xA0 UART4/COM4 0x02E8 0x9 = IRQ11 0xA8 UART9/COM2...
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Page 35: Programmable Led
Programming Information for Hardware Interfaces Table 29: Baud Rates, Divisors, and Base Clock and Ratio Selection for UARTs PCI register Baud rate "Crystal" Decimal Standard or setting Clock ratio (bps) base clock divisor high-speed (32-bits) [Note] 1200 1.8432 MHz 1/16 Standard 00Axyyyy 2400... -
Page 36: Appendix A - References
Overview of http://www.vortex86.com/?p=16 Vortex86DX2 Data sheet for ILAN9512 – USB 2.0 Hub and http://ww1.microchip.com/downloads/en/DeviceDoc/9512.pdf 10/100 Ethernet Controller Data sheet for Microchip http://www.versalogic.com/support/Downloads/PDF/MCP23S17%20IO%20expand MCP23S17 – er.pdf 16-Bit I/O expander with serial interface *** End of document *** EPM-19 Programmer’s Reference Manual...
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