Lvds Flat Panel Display Connector - VersaLogic Python EBX-11 Reference Manual

LVDS F P
LAT ANEL
The integrated LVDS Flat Panel Display in the EBX-11 is an ANSI/TIA/EIA-644-1995
specification-compliant interface. It can support up to 24 bits of RGB pixel data plus 3 bits of
timing control (HSYNC/VSYNC/DE) on the 4 differential data output pairs. The LVDS clock
frequency ranges from 25 MHz to 112 MHz.
CMOS Setup provides several options for standard LVDS Flat Panel types. If these options do
not match the requirements of the panel you are attempting to use, contact
Support@VersaLogic.com
The 3.3V power provided to pins 19 and 20 of J9 is protected by a 1 Amp fuse.
See the connector location diagram on page 16 for pin and connector location information.
EBX-11 Reference manual
D C
ISPLAY ONNECTOR
for a custom video BIOS.
Table 18: LVDS Flat Panel Display Pinout
J9 Signal
Pin Name
1 GND
2 NC
3 LVDSA3
4 LVDSA3#
5 GND
6 LVFSCLK0
7 LVDSCLK0#
8 GND
9 LVDSA2
10 LVDSA2#
11 GND
12 LVDSA1
13 LVDSA1#
14 GND
15 LVDSA0
16 LVDSA0#
17 GND
18 GND
19 +3.3V
20 +3.3V
Interfaces and Connectors
Function
Ground
Not Connected
Diff. Data (+)
Diff. Data 3 (-)
Ground
Differential Clock (+)
Differential Clock (-)
Ground
Diff. Data 2 (+)
Diff. Data 2 (-)
Ground
Diff. Data 1 (+)
Diff. Data 1 (-)
Ground
Diff. Data 0 (+)
Diff. Data 0 (-)
Ground
Ground
Protected Power Supply
Protected Power Supply
40