VersaLogic Python EBX-11 Reference Manual page 3

Product Release Notes
Rev 6 Release

BIOS updated to Rev. 5.3.102 to add an option to turn off periodic System Management Interrupt.

Reset circuit modified to address isolated booting issues.

SPI interface improved in 6.00 PLD. SPI register set modified for ease of programming. Customers
requiring previous SPI register configuration can retain 5.xx PLD. See
the differences between the 6.00 and 5.xx SPI interfaces.

BIOS updated to Rev. 5.3.101 to correct the operation of the BIOS reflash utility.
Rev 5 Release

Production release. See KnowledgeBase article
release. See

EBX-11h Rev. 5.01 Released Nov. 2007.
Rev 4 Release
Beta release. Note: This release contained a nonstandard Digital I/O signaling on the J5 connector. See J5
I/O Connector on page 27 for details. The pinout will be corrected with the Rev. 5 release.
Rev 3 Release
Pre-production only. No customer releases.
Rev 2 Release
Pre-production only. No customer releases.
Rev 1 Release
Pre-production only. No customer releases.
Support
The EBX-11 support page, at http://www.versalogic.com/private/pythonsupport.asp, contains additional
information and resources for this product including:

Reference Manual (PDF format)

Operating system information and software drivers

Data sheets and manufacturers' links for chips used in this product

BIOS information and upgrades

Utility routines and benchmark software
This is a private page for EBX-11 users that can be accessed only be entering this address directly. It
cannot be reached from the VersaLogic homepage.
The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with your
VersaLogic product.
EBX-11 Reference Manual
VT1527 for instructions on updating Rev. 4 boards with the Rev. 5 PLD code.
VersaTech KnowledgeBase
VT1563
VT1524 for a list of changes made for this
for a description of
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