Pcie - Nvidia Jetson TX2 Manual

One for each of the USB 3.0 input lines (RX_+/-)

5.2 PCIe

Jetson TX2/TX2i contains a PCIe (PEX) controller that supports up to 5 lanes, and 3 Root-Port (RP) controllers.
Figure 17. PCIe Connection Example
Jetson TX2/TX2i
Tegra - PCIe
PEX
PEX_CLK3_P
PEX_CLK3_N
PEX_TX0P
PEX_TX0N
PEX_RX0P
PEX_RX0N
PEX_CLK1_P
PEX_CLK1_N
PEX_TX1P
PEX_TX1N
PEX_RX1P
PEX_RX1N
PEX_TX2P
PEX_TX2N
PEX_RX2P
PEX_RX2N
PEX_TX3P
PEX_TX3N
PEX_RX3P
PEX_RX3N
PEX_TX4P
PEX_TX4N
PEX_RX4P
PEX_RX4N
PEX_CLK2_P
PEX_CLK2_N
PEX PEX_L0_CLKREQ_N
PEX_L0_RST_N
Control
PEX_L1_CLKREQ_N
PEX_L1_RST_N
PEX_L2_CLKREQ_N
PEX_L2_RST_N
PEX_WAKE_N
PCIE Design Guidelines
Table 23. PCIE Interface Signal Routing Requirements
Parameter
Specification
Data Rate / UI Period
Configuration / Device Organization
Topology
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Near the module connector.
Mux
(Default)
SEL
Tegra
LS
QSPI_IO2
Mux
PMIC
SEL
GPIO7
Requirement
5.0 / 200
1
Point-point
PEX1_REFCLK+
B4 5
PEX1_REFCLK–
B4 6
0.1uF
PEX1_TX+
E41
0.1uF
PEX1_TX–
E42
PEX1_RX+
H41
PEX1_RX–
H42
USB_SS0_TX+
C43
USB_SS0_TX–
C44
USB 3.0 (Port #1)
USB_SS0_RX+
F43
USB_SS0_RX–
F44
PEX0_REFCLK+
A44
PEX0_REFCLK–
A45
0.1uF
PEX_RFU_T X+
D39
0.1uF
PEX_RFU_T X–
D40
PEX_RFU_RX+
G39
PEX_RFU_RX–
G40
0.1uF
USB_SS1_TX+
D42
0.1uF
USB_SS1_TX–
D43
USB_SS1_RX+
G42
USB_SS1_RX–
G43
0.1uF
PEX2_TX+
C40
0.1uF
PEX2_TX–
C41
PEX2_RX+
F40
PEX2_RX–
F41
0.1uF
PEX0_TX+
E44
0.1uF
PEX0_TX–
E45
PEX0_RX+
H44
PEX0_RX–
H45
PEX2_REFCLK+
A41
PEX2_REFCLK–
A42
VDD_3V3_SYS
PEX0_CLKREQ#
C48
PEX0_RST#
C49
PEX2_CLKREQ#
C46
PEX2_RST#
D49
SATA_DEV_SLP
D47
PEX1_CLKREQ#
C47
PEX1_RST#
E50
PEX_WAKE#
D48
Units
Gbps / ps
Load
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
PCIe – Single Lane (IF #2) or
(USB 3.0 Port #0). Used for M.2
Connector on Carrier Board
PCIe IF #0 Lane 3
Default: PCIe x1
(only PEX2_TX/RX lane used)
PCIe IF #0 Lane 1 Alternate: PCIe x4
(Routed to PCIe Connector on
Carrier Board)
PCIe IF #0 Lane 2
PCIe IF #0 Lane 0
Optionally used with PCIe
IF x1 on PEX2_TX/RX (PCIe
IF #1).
Control for PCIe
IF #0 Lanes
Control for PCIe
IF #1 Lane
Control for PCIe
IF #2 Lane
Shared
Notes
2.5GHz, half-rate architecture
Unidirectional, differential
30