Nvidia Jetson TX2 Manual page 68

Pin # Module Pin Name
D8 UART7_TX
Table 76. UART Interface Mapping
Module Pins (Tegra Functions)
UART0 (UART1)
UART1 (UART3)
UART2 (UART2)
UART3 (UART4)
UART7 (UART7)
Figure 41. UART Connections
Jetson TX2/TX2i
Tegra – UART
AO UART3_TX
UART3_RX
UART3_RTS_N
UART3_CTS_N
UART7_TX
UART7_RX
CONN
Jet son TX2
UART4_TX
UART4_RX
UART4_RTS_N
UART4_CTS_N
UART4_TX
UART4_RX
Jetson TX2i
UART4_RTS_N
UART4_CTS_N
DEBUG
UART1_TX
UART1_RX
UART1_RTS_N
UART1_CTS_N
UART2_TX
UART
UART2_RX
UART2_RTS_N
UART2_CTS_N
Note: Care should be taken when using UART pins that are associated with Tegra straps. See Strapping Pins section for details.
Table 77. UART Signal Connections
Ball Name Type
UART[7,3:0]_TX
UART[7,3:0]_RX
UART[3:0]_CTS#
UART[3:0]_RTS#
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Tegra Signal Usage/Description
UART7_TX UART 7 Transmit
I/O Block
DEBUG
AO
UART
CONN
AO
(RAM_CODE1 Strap) UART 1_TX
(RAM_CODE1 Strap) RSVD
Mux
WiFi / BT on
Jetson TX2
(RAM_CODE0 Strap) UART 0_RTS#
Termination
O
I
I
O
Usage on the Carrier
Board
Typical Usage
Debug
Serial Port
M.2 socket for external WLAN / BT
Jetson TX2
-
Misc. Available if not used for on-module WLAN
/ BT (selected by on-module multiplexor)
Jetson TX2i
-
Misc (no mux inv olved)
nd
2 Debug/Misc.
D9
UART 1_RX
D10
UART 1_RTS#
E9
UART 1_CTS#
E10
UART 7_TX_AP
D8
RSVD UART 7_RX_AP
D5
UART3_TX
H10
UART 3_RX
H9
UART 3_RTS#
G10
UART 3_CTS#
G9
UART 3_TX
H10
UART 3_RX
H9
UART 3_RTS#
G10
UART3_CTS#
G9
UART0_TX
H12
UART0_RX
G12
G11
UART 0_CTS#
H11
UART 2_TX
B1 6
UART 2_RX
B1 5
UART2_RTS#
A16
UART2_CTS#
A15
Description
UART Transmit: Connect to Peripheral RXD pin of device
UART Receive: Connect to Peripheral TXD pin of device
UART Clear to Send: Connect to Peripheral RTS_N pin of device
UART Request to Send: Connect to Peripheral CTS pin of device
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Direction
Output
Serial Port,
etc.
Misc.
Misc.
Misc.
Used for
Debug, etc.
M.2 Conn.
nd
(2 WiFi/Bt)
Pin Type
CMOS – 1.8V
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