Debug - Nvidia Jetson TX2 Manual

12.6 Debug

Figure 44. Debug Connections
Jetson TX2/TX2i
Tegra
DEBUG
JTAG_TMS
JTAG_TDI
JTAG_TCK
JTAG_TDO
JTAG_TRST_N
NVJTAG_SEL
UART1_TXD
UART1_RXD
UART1_RTS_N
UART1_CTS_N
DP
UART7_TX
UART7_RX
Notes:
JTAG_GP1 (Tegra NVJTAG_SEL) is left unconnected (pulled down on module) for normal operation and pulled to 1.8V for
1.
Boundary Scan Mode.
If level shifter is implemented, pull-ups are required the RX & CTS lines on the non-Tegra side of the level shifter. This is
2.
required to keep the inputs from floating and toggling when no device is connected to the debug UART.
Check preferred JTAG debugger documentation for JTAG PU/PD reco mmendations.
3.
12.6.1 JTAG
JTAG is not required, but may be useful for new design bring-up or for Boundary Scan.
Table 83. JTAG Pin Descriptions
Pin # Module Pin Name
B13 JTAG_GP0
A11 JTAG_GP1
A14 JTAG_RTCK
B11 JTAG_TCK
B12 JTAG_TDI
A13 JTAG_TDO
A12 JTAG_TMS
Table 84. JTAG Signal Connections
Module Pin Type
(function) Name
JTAG_TMS I
JTAG_TCK I
JTAG_TDO O
JTAG_TDI I
JTAG_RTCK I
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
JTAG_RTCK
JTAG_T MS
JTAG_T DI
JTAG_TCK
JTAG_TDO
JTAG_GP0
JTAG_GP1
0.1uF
RESET_IN
To PMIC
UART0_TX
UART 0_RX
UART 0_RTS#
UART0_CTS#
RSVD
RSVD
Tegra Signal Usage/Description
JTAG_TRST_N JTAG Test Reset
JTAG General Purpose 1. Pulled low on
module for normal operation & pulled
NVJTAG_SEL
high by test device for Boundary Scan
test mode.
− JTAG Return Clock
JTAG_TCK JTAG Test Clock
JTAG_TDI JTAG Test Data In
JTAG_TD0 JTAG Test Data Out
JTAG_TMS JTAG Test Mode Select
Termination
100kΩ to GND (on the module)
VDD_1V8
A14
A12
B1 2
B1 1
A13
B1 3
0Ω
A11
See Note 1
A47
VDD_1V8 VDD_3V3_SYS
H12
Level
G12
Shifter
G11
H11
See Note 2
D8
D5
Usage on the Carrier
Board
JTAG Header & Debug
Connector
JTAG
JTAG Header & Debug
Connector
Description
JTAG Mode Select: Connect to TMS pin of connector
JTAG Clock: Connect to TCK pin of connector
JTAG Data Out: Connect to TDO pin of connector
JTAG Data In: Connect to TDI pin of connector
JTAG Return Clock: Connect to RTCK pin of connector
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Optional JTAG
connections
RTCK
TMS
TDI
TCLK
TDO
TRST_N
RST
For Debug Use
Direction
Input CMOS – 1.8V
Input CMOS – 1.8V
Input CMOS – 1.8V
Input CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Pin Type
71