Nvidia Jetson TX2 Manual page 59

Figure 32. I2S & Codec Clock/Control Connections
Jetson TX2/TX2i
Tegra
AUDIO AUD_MCLK
GPIO_AUD1
DAP1_SCLK
DAP1_FS
DAP1_DOUT
DAP1_DIN
AUDIO_HV
GPIO_AUD0
DMIC2_DAT
DMIC1_CLK
DMIC2_CLK
DMIC1_DAT
DAP4_SCLK
DAP4_FS
DAP4_DOUT
DAP4_DIN
DMIC_HV
GPIO_PQ0
GPIO_PQ3
GPIO_PQ1
GPIO_PQ2
CONN
DAP2_SCLK
DAP2_FS
DAP2_DOUT
DAP2_DIN
Note:
The I2S interfaces can be used in either Master or Slave mode.
-
A capacitor from DAPn_FS to GND is recommended if Tegra an I2S slave & the edge_cntrl configuration = 1 (SDATA
-
driven on positive edge of SCLK). The value of the capacitor should be chosen to provide a minimum of 2ns hold time for
the DAPn_FS edge after the rising edge of DAPn_SCLK.
I2S Design Guidelines
Table 61. I2S Interface Signal Routing Requirements
Parameter
Configuration / Device Organization
Max Loading
Reference plane
Breakout Region Impedance
Trace Impedance
Via proximity (Signal to reference)
Trace spacing
Max Trace Delay
Max Trace Delay Skew between SCLK & SDATA_OUT/IN
Note: Up to 4 signal Vias can share a single GND return Via
Table 62. I2S & Codec Clock/Control Signal Connections
Module Pin Name Type
I2S[3:0]_SCLK I/O
I2S[3:0]_LRCK I/O
I2S[3:0]_SDATA_OUT
I/O
I2S[3:0]_SDATA_IN I
AUD_MCLK O
GPIO19_AUD_RST O
GPIO20_AUD_INT I
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Tegra
Function
75Ω
AUDIO_MCLK
GPIO19_AUD_RST
75Ω
I2S1_CLK I2S0_CLK
I2S1_LRCK I2S0_LRCK
I2S1_SDOUT I2S0_SDOUT
I2S1_SDIN I2S0_SDIN
GPIO20_AUD_INT
75Ω
I2S3_CLK I2S2_CLK
I2S3_LRCK I2S2_LRCK
I2S3_SDOUT I2S2_SDOUT
I2S3_SDIN I2S2_SDIN
120Ω@
I2S4_CLK I2S3_CLK
I2S4_LRCK I2S3_LRCK
I2S4_SDOUT I2S3_SDOUT
I2S4_SDIN I2S3_SDIN
120Ω@
I2S6_CLK
Primary
I2S6_LRCK
WiFi/BT
I2S6_SDOUT
(TX2 only)
I2S6_SDIN
I2S2_CLK I2S1_CLK
I2S2_LRCK I2S1_LRCK
I2S2_SDOUT I2S1_SDOUT
I2S2_SDIN I2S1_SDIN
Requirement
1
8
GND
Min width/spacing
50
< 3.8 (24)
Microstrip or Stripline 2x
3600 (~22)
250 (~1.6")
Termination
I2S[2,0]_CLK have 75Ω beads & I2S3_CLK
has a 120Ω Bead in series (on the module).
75Ω Beads in series (on the module).
Nvidia
Carrier Board
Net Name
Audio
AUDIO_I2S_MCLK
F1
GPIO_X1_AUD Codec
F2
DAP1_SCLK_AP
G2
DAP1_F S_AP
H1
DAP1_DOUT_AP
H2
DAP1_DIN_AP
G1
AUD_INT
H3
DAP3_SCLK_AP
nd
G5
2 WiFi/BT,
DAP3_FS_AP
H5
Modem
DAP3_DOUT_AP
H6
DAP3_DIN_AP
G6
DAP4_SCLK_AP
E6
Misc
DAP4_FS_AP
F5
DAP4_DOUT_AP
F6
DAP4_DIN_AP
E5
DAP2_SCLK_AP
C15
Misc
DAP2_FS_AP
D13
DAP2_DOUT_AP
D14
DAP2_DIN_AP
C14
Units
mm (ps)
dielectric
ps (in)
ps (in)
Description
I2S Serial Clock: Connect to I2S/PCM CLK pin of audio device.
I2S Left/Right Clock: Connect to Left/Right Clock pin of audio device.
I2S Data Output: Connect to Data Input pin of audio device.
I2S Data Input: Connect to Data Output pin of audio device.
Audio Codec Master Clock: Connect to clock pin of Audio Codec.
Audio Reset: Connect to reset pin of Audio Codec.
Audio Interrupt: Connect to interrupt pin of Audio Codec.
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Notes
load
pF
Ω ±20%
See Note 1
59