Nvidia Jetson TX2 Manual page 40

Figure 23: Display Backlight/Control Connections
Jetson TX2/TX2i
Tegra
SYS GPIO_DIS3
GPIO_DIS0
GPIO_DIS5
GPIO_DIS1
eDP
GPIO_EDP0
MIPI DSI / CSI Design Guidelines
Table 35. MIPI DSI & CSI Interface Signal Routing Requirements
Parameter
Max Frequency/Data Rate (per data lane)
Number of Loads
Max Loading (per pin)
Reference plane
Breakout Region Impedance (Single Ended)
Max PCB breakout delay
Trace Impedance
Via proximity (Signal to reference)
Trace spacing
Max Trace Delay
Max Intra-pair Skew
Max Trace Delay Skew between DQ & CLK
Keep critical DSI/CSI related traces including DSI/CSI clock/data traces & RDN/RUP traces away from other signal traces or unrelated power
traces/areas or power supply components
Note: If PWR, 0.01uF decoupling cap required for return current
1.
Up to 4 signal Vias can share a single GND return Via
2.
If routing to device includes a flex or 2nd PCB, the max trace & skew calculations must include all the PCBs/flex routing
3.
MIPI DSI / CSI Connection Guidelines
Table 36. MIPI DSI Signal Connections
Module Pin Name
DSI[3:0]_CK+/–
DSI[3:0]_D[1:0]+/–
LCD_TE
LCD_BL_EN
LCD[1:0]_BKLT_PWM
LCD_VDD_EN
Table 37. Recommended DSI observation (test) points for initial boards
Test Points Recommended
One for each signal line.
Note: Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
LCD_BKLT_EN
LCD0_BKLT_PWM
LCD1_BKLT_PWM
LCD_TE
LCD_VDD_EN
Requirement
HS (DSI) 0.75 / 1.5
HS (CSI) 1.25 / 2.5
LP 10
1
10
GND
45-50
48
Diff pair / Single Ended 90-100 / 45-50
< 3.8 (24)
Microstrip / Stripline 2x / 2x
1 Gbps 1100
1.5 Gbps 800
2.5 Gbps 350
1
5
Type Termination
DIFF OUT
DIFF OUT
I
O
O
O
B2 8
Backlight
B2 7
Control
A24
A25 Tearing Effect
Display
B2 6
Power Enable
GHz/Gbps
mm (ps)
dielectric
Description
DSI Differential Clocks: Connect to CLKn & CLKp pins of receiver. See
connection diagrams for Dual & Split Link Mode configurations.
DSI Differential Data Lanes: Connect to Dn & Dp pins of DSI display. See
connection diagrams for Dual & Split Link Mode configurations.
LCD Tearing Effect: Connect to LCD Tearing Effect pin if supported
LCD Backlight Enable: Connect to LCD backlight solution enable if supported
LCD Backlight Pulse Width Modulation: Connect to LCD backlight solution PWM
input if supported
LCD Power Enable: Connect as necessary to enable appropriate Display power
supply(ies).
Location
Near display. Panel connector pins can be used if accessible.
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Units Notes
MHz
load
pF
See Note 1
Ω ±15%
ps
Ω
See Note 2
See Note 3
mm (ps)
See Note 3
ps
See Note 3
ps
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