Nvidia Jetson TX2 Manual page 45

Table 41. eDP Signal Connections
Module Pin Name Type
DPx_TX[3:0]+/– O
DPx_AUX+/– I/OD
DPx_HPD I
Table 42. Recommended eDP/DP observation (test) points for initial boards
Test Points Recommended
One for each signal line.
Note: Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces
7.2.2 HDMI
A standard DP 1.2a or HDMI V2.0 interface is supported. These share the same set of interface pins, so either Display Port or
HDMI can be supported natively. Dual-Mode DisplayPort(DP++ ) can be supported, in w hich the DisplayPort connector logically
outputs TMDS signaling to a DP-to-HDMI dongle.
7.2.3 HDMI
Figure 26: HDMI Connection Example
Jetson TX2/TX2i
Tegra - HDMI
eDP
DP_AUX_CH1_HPD
DP_AUX_CH1_P
DP_AUX_CH1_N
HDMI_CEC
HDMI_DPx
HDMI_DPx_TXDP0
HDMI_DPx_TXDN0
HDMI_DPx_TXDP1
HDMI_DPx_TXDN1
HDMI_DPx_TXDP2
HDMI_DPx_TXDN2
HDMI_DPx_TXDP3
HDMI_DPx_TXDN3
Note: Level shifters required on DDC/HPD. Jetson TX2/TX2i pads are not 5V tolerant & cannot directly meet HDMI V
1.
requirements. HPD level shifter can be non-inverting or inverting.
If EMI/ESD devices are necessary, they must be tuned to minimize the impact to signal quality, which must meet the
2.
timing & electrical requirements of the HDMI specification for the modes to be supported. See requirements &
recommendations in the related sections of the HDMI Interface Signal Routing Requirements table.
The HDMI_DP_TXx pads are native DP pads & require series AC capacitors (AC
3.
compliant. The 499Ω, 1% pull-downs must be disabled when Tegra is off to meet the HDMI V
enable to the FET, enables the pull-downs when the HDMI interface is to be used. Chokes between pull-downs & FET are
required for Standard Technology designs and recommended for HDI designs.
Series resistors R
4.
Tegra supports a single CEC controller that can be associated with one of the display output heads.
5.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Termination
Series 0.1uF capacitors on all lines
Series 0.1uF capacitors
DP0/DP1
DPx_HPD
B3 6/A33
DPx_AUX_CH+
B3 5/A35
DPx_AUX_CH–
B3 4/A34
HDMI_CEC
B3 3
TXD0_P
DPx_TX2
G37/D37
TXD0_N
DPx_TX2
G36/D36
TXD1_P
DPx_TX1
F38/C3 8
TXD1_N
DPx_TX1
F37/C3 7
TXD2_P
DPx_TX0
H39/E3 9
TXD2_N
DPx_TX
H38/E3 8
TXC_P
DPx_TX3
H36/E3 6
TXC_N
DPx_TX3
H35/E3 5
are required. See the R section of the HDMI Interface Signal Routing Requirements table for details.
S S
Description
eDP/DP Differential CLK/Data Lanes: Connect to matching pins on display
connector. See DP/HDMI Pin Mapping & connection diagram for details.
eDP/DP: Auxiliary Channels: Connect to AUX_CH+/– on display connector.
eDP/DP: Hot Plug Detect: Connect to HPD pin on display connector.
Location
Near display connector. Connector pins can be used if accessible.
VDD_1V8 VDD_3V3_SYS VDD_5V0_HDMI
See Note 1
Level Shifter
Level Shifter
CEC Gating
Circuitry
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
,
See Note 3
1%
00
@100MHz
Enable
FET
5V0_HDMI_EN
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
HDMI Connector
0.1uF 10uF
100kΩ
EMI
See Note 2
ESD
R
S
R
S
R
S
R
S
CMC
R
S
R
S
R
S
R
S
See
See
Note 2
ESD Note 4
) & pull-downs (R ) to be HDMI
CAP PD
requirement. The
OFF
+5V
HPD
SCL
SDA
CEC
D0+
D0-
D1+
D1-
D2+
D2-
CK+
CK-
/V
IL IH
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