Quectel RM502Q-GL Hardware Design page 35

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The reset timing is illustrated by the following figure.
VCC(H)
RESET#
FCPO#(H)
RFFE_VIO_1V8
USIM_VDD
Module Status
NOTE: The host GPIO only needs to control module RESET# to reset the module.
Table 13: Reset Timing of the Module
Symbol
Min.
T
200 ms
RST#-USIM
T
200 ms
RST#
RM502Q-GL_Hardware_Design
S1
TVS
C1
33 pF
200-980 ms
NOTE: The capacitor C1 is recommended to be less than 47 pF.
Figure 13: Reference Circuit of RESET# with Button
3.7 V
1.8 V
≥ 1.19 V
V
IH
1.8 V
T
RST#-USIM
1.8 V or 3.0 V
Running
Figure 14: Reset Timing of the Module
Typ.
Max.
400 ms
980 ms
Module
VDD 1.8V
R1
100k
RESET#
67
Resetting
200 ms ≤ T
RST#
Comment
(U)SIM card turn-off time.
T
980 ms will cause repeated reset.
RST#
5G Module Series
RM502Q-GL Hardware Design
PMIC
≤ 980 ms
Restarting
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