Quectel RM502Q-GL Hardware Design page 23

47 PCIE_RX_M
48 USIM2_VDD
49 PCIE_RX_P
50 PCIE_RST_N
51 GND
52 PCIE_CLKREQ_N
53 PCIE_REFCLK_M
54 PCIE_WAKE_N
55 PCIE_REFCLK_P
2)
56 RFFE_CLK
57 GND
2)
58 RFFE_DATA
59 LAA_TX_EN*
60 WLAN_TX_EN*
61 ANTCTL1
62 COEX_RXD*
63 ANTCTL2
64 COEX_TXD*
65 RFFE_VIO_1V8
1)
66 USIM1_DET
RM502Q-GL_Hardware_Design
AI PCIe receive (-)
Power supply for
PO
(U)SIM2 card
AI PCIe receive (+)
PCIe reset.
DI, OD
Active LOW.
Ground
PCIe clock request.
DO, OD
Active LOW.
PCIe reference clock
AIO
(-)
PCIe wake up
DO, OD
Active LOW.
PCIe reference clock
AIO
(+)
Used for external
DO, PD
MIPI IC control
Used for external
DO, PD
MIPI IC control
Notification from SDR
DO to WLAN while LTE
transmitting
Notification from
DI WLAN to SDR while
transmitting
DO, PD Antenna GPIO control 1.8 V
LTE/WLAN
DI, PD
coexistence receive
DO, PD Antenna GPIO control 1.8 V
LTE/WLAN
DO, PD
coexistence transmit
Power supply for
PO
RFFE
(U)SIM1 card
DI, PU
hot-plug detect
5G Module Series
RM502Q-GL Hardware Design
1.8/3.0 V
USIM1_VDD
1.8/3.0 V
1.8 V
Ground
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
Maximum output
1.8 V
current: 50 mA
1.8 V
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