Quectel RM502Q-GL Hardware Design page 22

26 W_DISABLE2#
27 GND
28 PCM_SYNC
29 USB_SS_TX_M
30 USIM1_RST
31 USB_SS_TX_P
32 USIM1_CLK
33 GND
34 USIM1_DATA
35 USB_SS_RX_M
36 USIM1_VDD
37 USB_SS_RX_P
38 SDX2AP_STATUS*
39 GND
1)
40 USIM2_DET
41 PCIE_TX_M
42 USIM2_DATA
43 PCIE_TX_P
44 USIM2_CLK
45 GND
46 USIM2_RST
RM502Q-GL_Hardware_Design
GNSS disable
DI, OD control.
Active LOW.
Ground
DIO, PD PCM data frame sync
USB 3.1 super-speed
AO
transmit (-)
DO, PD (U)SIM1 card reset
USB 3.1 super-speed
AO
transmit (+)
DO, PD (U)SIM1 card clock
Ground
DIO, PU (U)SIM1 card data
USB 3.1 super-speed
AI
receive (-)
Power supply for
PO
(U)SIM1 card
USB 3.1 super-speed
AI
receive (+)
Status indication to
DO, PD
AP
Ground
(U)SIM2 card
DI, PU
hot-plug detect
AO PCIe transmit (-)
DIO, PU (U)SIM2 card data
AO PCIe transmit (+)
DO, PD (U)SIM2 card clock
Ground
DO, PD (U)SIM2 card reset
5G Module Series
RM502Q-GL Hardware Design
1.8/3.3 V
1.8 V
USIM1_VDD
1.8/3.0 V
USIM1_VDD
1.8/3.0 V
USIM1_VDD
1.8/3.0 V
USIM1_VDD
1.8/3.0 V
1.8 V
1.8 V
Require
differential
impedance of
85 Ω
USIM_VDD
1.8/3.0 V
USIM1_VDD
1.8/3.0 V
USIM1_VDD
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