Pin Definition Of Pcie - Quectel RM502Q-GL Hardware Design

NOTES
1. The underlined value is the default parameter value.
2. For more details about the command, see document [4].

4.3.2. Pin Definition of PCIe

The following table shows the pin definition of PCIe interface.
Table 16: Pin Definition of PCIe Interface
Pin No. Pin Name
55 PCIE_REFCLK_P
53 PCIE_REFCLK_M
49 PCIE_RX_P
47 PCIE_RX_M
43 PCIE_TX_P
41 PCIE_TX_M
50 PCIE_RST_N
52 PCIE_CLKREQ_N
54 PCIE_WAKE_N
RM502Q-GL_Hardware_Design
I/O Description
AIO PCIe reference clock (+)
AIO PCIe reference clock (-)
AI PCIe receive (+)
AI PCIe receive (-)
AO PCIe transmit (+)
AO PCIe transmit (-)
PCIe reset.
DI, OD
Active LOW
PCIe clock request.
DO, OD
Active LOW
PCIe wake up
DO, OD
Active LOW
5G Module Series
RM502Q-GL Hardware Design
Comment
100 MHz.
Require differential
impedance of 85 Ω
Require differential
impedance of 85 Ω
Require differential
impedance of 85 Ω
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