HP 81200 User Manual page 147

How to Specify Events and Reactions to Events
Detection and Reaction Times
HP 81200 Data Generator/Analyzer Platform User Guide, Revision 2.1
– A bitstream error detected by one of the modules (not available in
capture-only or BER mode).
3 Decide on the priorities.
– Do you need immediate reaction?
– In case of deferred reaction: Which event must be serviced under all
circumstances? What is the minimal block length to guarantee
reaction at the end of the block?
What You Need to Consider Before Using Events
There is of course a delay between the occurrence of an event and its
recognition. There is also a delay between the recognition of an event and
the reaction to that event.
Detection of and reaction to events is controlled by an internal sequencer
clock. The port-dependent frequency of that clock is:
Clk _freq = system clock frequency / blocklength granularity.
p
The maximal sequencer clock frequency is hence 41.67 MHz,
corresponding to a period of 24 ns. If you had set a system clock rate of
100 MHz and a blocklength granularity of 4, the sequencer clock frequency
would be 25 MHz, corresponding to a period of 40 ns.
The delays are illustrated in the figure below.
Figure 71 Delays Between Event Occurrence, Detection, and Reaction
Creating the Stream of Generated and Expected Data
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