Infineon AIROC CYBLE-343072-02 Manual page 15

AIROC™ Bluetooth® LE module
Module connections
Table 4 Pin assignments
Module pad Pad
name number
HOST_WAKE
NA
NA
XRES
Table 5 GPIO pin descriptions
Module Silicon
Pad
pad
number
name name
P0 10
P1 9
P2 34
P3 35
P4 37
P5 38
P6 39
P7 40
P8 41
P9 17
Notes
4. The CYBLE-3x307x-02 contains a single SPI (SPI1) peripheral supporting both master or slave configura-
tions. SPI2 is used for on-module serial memory interface.
5. In Master mode, any available GPIO can be configured as SPI1_CS. This function is not explicitly shown in
Table 20.
Preliminary Datasheet
(continued)
Silicon pin name
36 BT_HOST_WAKE
NA BT_RF
NA JTAG_SEL
3 RST_N
Direction POR
pin
Default state
P0 Input Floating
P1 Input Floating
P2 Input Floating
P3 Input Floating
P4 Input Floating
P5 Input Floating
P6 Input Floating
P7 Input Floating
P8 Input Floating
P9 Input Floating
Power
I/O
domain
O VDDO
I/O PAVDD2P5
– –
I VDDO
Power
Default alternate function description
domain
VDDO GPIO: P0
A/D converter input 29
Note Not available during TM1 = 1.
VDDO GPIO: P1
A/D converter input 28
VDDO GPIO: P2
VDDO GPIO: P3
VDDO GPIO: P4
VDDO GPIO: P5
VDDO GPIO: P6
VDDO GPIO: P7
VDDO GPIO: P8
A/D converter input 27
VDDO GPIO: P9
A/D converter input 26
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Description
Host wake-up. This is a signal from
the Bluetooth® device to the host
indicating that the Bluetooth®
device requires attention.
• Asserted: Host device must wake
up or remain awake
• Deasserted: Host device may
sleep when sleep awake criteria
is met. The polarity of this signal
is software configurable and can
be asserted high or low.
RF antenna port
ARM JTAG debug mode control:
connect to GND for all applications
Active-low system reset with
open-drain output and internal
pull-up resistor
002-33419 Rev. **
2021-07-22