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AIROC™ Bluetooth® LE module
Peripheral and communication interfaces
8
Peripheral and communication interfaces
2
8.1
I
C communication interface
The CYBLE-3x307x-02 provides a 2-pin master I
mation from an external EEPROM or to communicate with peripherals such as track-ball or touch-pad modules,
and motion tracking ICs used in mouse devices. This interface is compatible with I
support multimaster capability or flexible wait-state insertion by either master or slave devices.
The following transfer clock rates are supported by the I
• 100 kHz
• 400 kHz
• 800 kHz (not a standard I
• 1 MHz (Compatibility with high-speed I
The following transfer types are supported by the I
• Read (Up to 8 bytes can be read)
• Write (Up to 8 bytes can be written)
• Read-then-Write (Up to 8 bytes can be read and up to 8 bytes can be written)
• Write-then-Read (Up to 8 bytes can be written and up to 8 bytes can be read)
Hardware controls the transfers, requiring minimal firmware setup and supervision.
The clock pad (I2C_SCL) and data pad 2 (I2C_SDA) are both open-drain I/O pins. Pull-up resistors, external to the
CYBLE-3x307x-02, are required on both the SCL and SDA pad for proper operation.
8.2
HCI UART interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from
57600 bps to 6 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected
via a vendor-specific UART HCI command. The CYBLE-3x307x-02 has a 1040-byte receive FIFO and a 1040-byte
transmit FIFO to support enhanced data rates. The interface supports the Bluetooth® UART HCI (H4) specifi-
cation. The default baud rate for H4 is 115.2 kbaud.
The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 6 Mbps.
The baud rate of the CYBLE-3x307x-02 UART is controlled by two values. The first is a UART clock divisor (set in
the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment
(set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half
of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART
clock cycles can be inserted into the end of each bit time.
Table 9
contains example values to generate common baud rates with a 24 MHz UART clock.
Table 9
Common baud rate examples, 24 MHz clock
Baud rate (bps)
3M
2M
1M
921600
460800
230400
Preliminary Datasheet
2
C interface, which can be used to retrieve configuration infor-
2
C-compatible speed.)
2
C-compatible devices is not guaranteed.)
Baud rate adjustment
High nibble
0xFF
0XFF
0X44
0x05
0x02
0x04
2
C:
2
C:
Low nibble
0xF8
High rate
0XF4
High rate
0XFF
Normal
0x05
Normal
0x02
Normal
0x04
Normal
25 of 58
2
C slave devices. I
Mode
Error (%)
0.00
0.00
0.00
0.16
0.16
0.16
002-33419 Rev. **
2
C does not
2021-07-22
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