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AIROC™ Bluetooth® LE module
Timing and AC characteristics
16.2
SPI timing
The SPI interface supports clock speeds up to 12 MHz
Table 19
and
Figure 14
3, respectively.
Table 19
SPI mode 0 and 2
Reference
Time from slave assert SPI_INT to master assert SPI_CSN
1
(DirectRead)
Time from master assert SPI_CSN to slave assert SPI_INT
2
(DirectWrite)
3
Time from master assert SPI_CSN to first clock edge
4
Setup time for MOSI data lines
5
Hold time for MOSI data lines
6
Time from last sample on MOSI/MISO to slave deassert SPI_INT
7
Time from slave deassert SPI_INT to master deassert SPI_CSN
8
Idle time between subsequent SPI transactions
SPI_CSN
SPI_INT
(DirectWrite)
SPI_INT
(DirectRead)
SPI_CLK
(Mode 0)
SPI_CLK
(Mode 2)
SPI_MOSI
SPI_MISO
Not Driven
Figure 14
SPI timing – mode 0 and 2
Preliminary Datasheet
show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and
Characteristics
1
2
First Bit
Second Bit
First Bit
Second Bit
39 of 58
Min
Max
0
0
20
8
½ SCK
8
½ SCK
0
100
0
1 SCK
5
Last bit
Not Driven
Last bit
002-33419 Rev. **
Unit
ns
2021-07-22
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