Figure B-3 Detailed Block Diagram - Sun Microsystems SPARCserver 1000 Service Manual

On-board
ethernet
and SCSI
Slot 1
Slot 2
Slot 3
B.3 Arbitration System
SBus
SPARC module
Page
High
table
speed
cache
plus
parity
SBus
Intf.
(SBI)
XBus
I/O Memory
Cache control
(IOC) (MQH)
DRAM
group
Figure B-3 Detailed Block Diagram
The SPARCserver 1000 supports a large number of devices that demand
ownership of system resources, including exclusive access to the system
backplane address and data bus. To prevent conflicts over access to resources,
SPARCserver 1000 has a two-tier arbitration system; one tier monitors the
boards; the other tier, which is higher, monitors the overall system.
Each system board has a board arbiter (BARB). The function of the BARB is to
determine which device (bus watcher (BW), memory queue handler (MQH), or
I/O cache (IOC)) is next in line to access the XDBus.
Functional Description
LEDS JTAG Control
SRAM TODC/NVRAM
UARTs EPROM
BBC2
BootBus
SPARC module
CPU CPU
Data Data
Addr Addr
Cache Cache
control control
XBus XBus
Bus Bus
watcher watcher
(BW) (BW)
DRAM
group
B
High
speed
cache
plus
parity
BIC
and
BARB
B-3